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Message-ID: <FA93EFB9-954B-421E-97B2-AE9E0A0A4216@redhat.com>
Date: Tue, 16 Sep 2025 20:16:57 +0200
From: Ivan Vecera <ivecera@...hat.com>
To: Jakub Kicinski <kuba@...nel.org>
CC: netdev@...r.kernel.org, Przemek Kitszel <przemyslaw.kitszel@...el.com>,
Prathosh Satish <Prathosh.Satish@...rochip.com>,
Jiri Pirko <jiri@...nulli.us>, "David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>, Paolo Abeni <pabeni@...hat.com>,
Simon Horman <horms@...nel.org>, Jonathan Corbet <corbet@....net>,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
Subject: Re: [PATCH net-next v2] dpll: zl3073x: Allow to use custom phase measure averaging factor
On September 16, 2025 1:46:41 AM GMT+02:00, Jakub Kicinski <kuba@...nel.org> wrote:
>cc: Arkadiusz
>
>On Thu, 11 Sep 2025 09:23:01 +0200 Ivan Vecera wrote:
>> The DPLL phase measurement block uses an exponential moving average,
>> calculated using the following equation:
>>
>> 2^N - 1 1
>> curr_avg = prev_avg * --------- + new_val * -----
>> 2^N 2^N
>>
>> Where curr_avg is phase offset reported by the firmware to the driver,
>> prev_avg is previous averaged value and new_val is currently measured
>> value for particular reference.
>>
>> New measurements are taken approximately 40 Hz or at the frequency of
>> the reference (whichever is lower).
>>
>> The driver currently uses the averaging factor N=2 which prioritizes
>> a fast response time to track dynamic changes in the phase. But for
>> applications requiring a very stable and precise reading of the average
>> phase offset, and where rapid changes are not expected, a higher factor
>> would be appropriate.
>>
>> Add devlink device parameter phase_offset_avg_factor to allow a user
>> set tune the averaging factor via devlink interface.
>
>Is averaging phase offset normal for DPLL devices?
I don't know... I expect that DPLL chips support phase offset
measurement but probably implementation specific.
>If it is we should probably add this to the official API.
The problem in case of this Microchip DPLL devices is that this
parameter is per ASIC. It is common for all DPLL channels
(devices) inside the chip. That's why I chose devlink.
>If it isn't we should probably default to smallest possible history?
Do you mean the default value?
Ivan
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