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Message-Id: <E1uytpf-00000006H2c-3hiU@rmk-PC.armlinux.org.uk>
Date: Wed, 17 Sep 2025 16:12:31 +0100
From: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
To: Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Andrew Lunn <andrew+netdev@...n.ch>,
Chen-Yu Tsai <wens@...e.org>,
"David S. Miller" <davem@...emloft.net>,
Drew Fustini <fustini@...nel.org>,
Emil Renner Berthing <kernel@...il.dk>,
Eric Dumazet <edumazet@...gle.com>,
Fabio Estevam <festevam@...il.com>,
Fu Wei <wefu@...hat.com>,
Guo Ren <guoren@...nel.org>,
imx@...ts.linux.dev,
Jakub Kicinski <kuba@...nel.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
linux-arm-kernel@...ts.infradead.org,
linux-riscv@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com,
linux-sunxi@...ts.linux.dev,
Maxime Chevallier <maxime.chevallier@...tlin.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Minda Chen <minda.chen@...rfivetech.com>,
Mohd Ayaan Anwar <mohd.anwar@....qualcomm.com>,
netdev@...r.kernel.org,
Paolo Abeni <pabeni@...hat.com>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Samuel Holland <samuel@...lland.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>,
Vladimir Zapolskiy <vz@...ia.com>
Subject: [PATCH net-next 07/10] net: stmmac: stm32: convert to use
phy_interface
dwmac-stm32 supports MII, RMII, GMII and RGMII interface modes,
selecting the dwmac core interface mode via bits 23:21 of the
SYSCFG register. The bit combinations are identical to the
dwmac phy_intf_sel_i signals.
None of the DTS files set "mac-mode", so mac_interface will be
identical to phy_interface.
Convert dwmac-stm32 to use phy_interface when determining the
interface mode rather than mac_interface.
Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 26 +++++++++----------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 77a04c4579c9..6c179911ef3f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -171,7 +171,7 @@ static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat)
{
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
- switch (plat_dat->mac_interface) {
+ switch (plat_dat->phy_interface) {
case PHY_INTERFACE_MODE_MII:
dwmac->enable_eth_ck = dwmac->ext_phyclk;
return 0;
@@ -193,7 +193,7 @@ static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat)
default:
dwmac->enable_eth_ck = false;
dev_err(dwmac->dev, "Mode %s not supported",
- phy_modes(plat_dat->mac_interface));
+ phy_modes(plat_dat->phy_interface));
return -EINVAL;
}
}
@@ -206,7 +206,7 @@ static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
if (!dwmac->enable_eth_ck)
return 0;
- switch (plat_dat->mac_interface) {
+ switch (plat_dat->phy_interface) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
if (clk_rate == ETH_CK_F_25M)
@@ -228,7 +228,7 @@ static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
}
dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz",
- phy_modes(plat_dat->mac_interface), clk_rate);
+ phy_modes(plat_dat->phy_interface), clk_rate);
return -EINVAL;
}
@@ -238,7 +238,7 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
u32 reg = dwmac->mode_reg;
int val = 0;
- switch (plat_dat->mac_interface) {
+ switch (plat_dat->phy_interface) {
case PHY_INTERFACE_MODE_MII:
/*
* STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
@@ -269,12 +269,12 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
break;
default:
dev_err(dwmac->dev, "Mode %s not supported",
- phy_modes(plat_dat->mac_interface));
+ phy_modes(plat_dat->phy_interface));
/* Do not manage others interfaces */
return -EINVAL;
}
- dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+ dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface));
/* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
@@ -294,7 +294,7 @@ static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
u32 reg = dwmac->mode_reg;
int val = 0;
- switch (plat_dat->mac_interface) {
+ switch (plat_dat->phy_interface) {
case PHY_INTERFACE_MODE_MII:
/* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */
break;
@@ -319,12 +319,12 @@ static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
break;
default:
dev_err(dwmac->dev, "Mode %s not supported",
- phy_modes(plat_dat->mac_interface));
+ phy_modes(plat_dat->phy_interface));
/* Do not manage others interfaces */
return -EINVAL;
}
- dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+ dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface));
/* Select PTP (IEEE1588) clock selection from RCC (ck_ker_ethxptp) */
val |= SYSCFG_ETHCR_ETH_PTP_CLK_SEL;
@@ -359,7 +359,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
u32 reg = dwmac->mode_reg;
int val;
- switch (plat_dat->mac_interface) {
+ switch (plat_dat->phy_interface) {
case PHY_INTERFACE_MODE_MII:
val = SYSCFG_MCU_ETH_SEL_MII;
break;
@@ -368,12 +368,12 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
break;
default:
dev_err(dwmac->dev, "Mode %s not supported",
- phy_modes(plat_dat->mac_interface));
+ phy_modes(plat_dat->phy_interface));
/* Do not manage others interfaces */
return -EINVAL;
}
- dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+ dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface));
return regmap_update_bits(dwmac->regmap, reg,
SYSCFG_MCU_ETH_MASK, val << 23);
--
2.47.3
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