netdev - Re: [PATCH v6 08/27] clk: mediatek: clk-mtk: Add MUX_DIV

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Message-ID: <175847362271.4354.15117894061507090727@lazor>
Date: Sun, 21 Sep 2025 09:53:42 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Laura Nao <laura.nao@...labora.com>, angelogioacchino.delregno@...labora.com, conor+dt@...nel.org, krzk+dt@...nel.org, matthias.bgg@...il.com, mturquette@...libre.com, p.zabel@...gutronix.de, richardcochran@...il.com, robh@...nel.org
Cc: guangjie.song@...iatek.com, wenst@...omium.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org, kernel@...labora.com, Laura Nao <laura.nao@...labora.com>, Nícolas F . R . A . Prado <nfraprado@...labora.com>
Subject: Re: [PATCH v6 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro

Quoting Laura Nao (2025-09-15 08:19:28)
> On MT8196, some clocks use one register for parent selection and
> gating, and a separate register for frequency division. Since composite
> clocks can combine a mux, divider, and gate in a single entity, add a
> macro to simplify registration of such clocks by combining parent
> selection, frequency scaling, and enable control into one definition.
> 
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@...labora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
> Signed-off-by: Laura Nao <laura.nao@...labora.com>
> ---

Applied to clk-next