[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <E1v1U6E-00000007HwL-0Z32@rmk-PC.armlinux.org.uk>
Date: Wed, 24 Sep 2025 19:20:18 +0100
From: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
To: Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>
Cc: Abhishek Chauhan <quic_abchauha@...cinc.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Alexis Lothore <alexis.lothore@...tlin.com>,
"Alexis Lothor__" <alexis.lothore@...tlin.com>,
Andrew Lunn <andrew+netdev@...n.ch>,
Boon Khai Ng <boon.khai.ng@...era.com>,
Choong Yong Liang <yong.liang.choong@...ux.intel.com>,
Daniel Machon <daniel.machon@...rochip.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Faizal Rahim <faizal.abdul.rahim@...ux.intel.com>,
Furong Xu <0x1207@...il.com>,
Huacai Chen <chenhuacai@...nel.org>,
Inochi Amaoto <inochiama@...il.com>,
Jacob Keller <jacob.e.keller@...el.com>,
Jakub Kicinski <kuba@...nel.org>,
"Jan Petrous (OSS)" <jan.petrous@....nxp.com>,
Jisheng Zhang <jszhang@...nel.org>,
Kees Cook <kees@...nel.org>,
Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Ley Foon Tan <leyfoon.tan@...rfivetech.com>,
linux-arm-kernel@...ts.infradead.org,
linux-arm-msm@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
Matthew Gerlach <matthew.gerlach@...era.com>,
Maxime Chevallier <maxime.chevallier@...tlin.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
netdev@...r.kernel.org,
Oleksij Rempel <o.rempel@...gutronix.de>,
Paolo Abeni <pabeni@...hat.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Rohan G Thomas <rohan.g.thomas@...era.com>,
Shenwei Wang <shenwei.wang@....com>,
Simon Horman <horms@...nel.org>,
Song Yoong Siang <yoong.siang.song@...el.com>,
Swathi K S <swathi.ks@...sung.com>,
Tiezhu Yang <yangtiezhu@...ngson.cn>,
Vinod Koul <vkoul@...nel.org>,
Vladimir Oltean <olteanv@...il.com>,
Vladimir Oltean <vladimir.oltean@....com>,
Yu-Chun Lin <eleanor15x@...il.com>
Subject: [PATCH RFC net-next 8/9] net: stmmac: only call stmmac_pcs_ctrl_ane()
for integrated SGMII PCS
The internal PCS registers only exist if the core is synthesized with
SGMII, TBI or RTBI support. They have no relevance for RGMII.
However, priv->hw->pcs contains a STMMAC_PCS_RGMII flag, which is set
if a PCS has been synthesized but we are operating in RGMII mode. As
the register has no effect for RGMII, there is no point calling
stmmac_pcs_ctrl_ane() in this case. Add a comment describing this
and make it conditional on STMMAC_PCS_SGMII.
Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index dff3bba83969..fb5a51d16897 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3519,7 +3519,11 @@ static int stmmac_hw_setup(struct net_device *dev)
}
}
- if (priv->hw->pcs)
+ /* The PCS control register is only relevant for SGMII, TBI and RTBI
+ * modes. We no longer support TBI or RTBI, so only configure this
+ * register when operating in SGMII mode with the integrated PCS.
+ */
+ if (priv->hw->pcs & STMMAC_PCS_SGMII)
stmmac_pcs_ctrl_ane(priv, 1, priv->hw->reverse_sgmii_enable);
/* set TX and RX rings length */
--
2.47.3
Powered by blists - more mailing lists