netdev - Re: [PATCH v18 03/20] cxl: Move pci generic code

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Message-ID: <d790f40d-c211-47d4-a76d-3cd43306cc67@amd.com>
Date: Thu, 25 Sep 2025 10:27:32 +0100
From: Alejandro Lucero Palau <alucerop@....com>
To: "Cheatham, Benjamin" <benjamin.cheatham@....com>,
 alejandro.lucero-palau@....com
Cc: Fan Ni <fan.ni@...sung.com>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>,
 Alison Schofield <alison.schofield@...el.com>, linux-cxl@...r.kernel.org,
 netdev@...r.kernel.org, dan.j.williams@...el.com, edward.cree@....com,
 davem@...emloft.net, kuba@...nel.org, pabeni@...hat.com,
 edumazet@...gle.com, dave.jiang@...el.com
Subject: Re: [PATCH v18 03/20] cxl: Move pci generic code


On 9/22/25 22:10, Cheatham, Benjamin wrote:
> On 9/18/2025 4:17 AM, alejandro.lucero-palau@....com wrote:
>> From: Alejandro Lucero <alucerop@....com>
>>
>> Inside cxl/core/pci.c there are helpers for CXL PCIe initialization
>> meanwhile cxl/pci.c implements the functionality for a Type3 device
>> initialization.
>>
>> Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be
>> exported and shared with CXL Type2 device initialization.
>>
>> Fix cxl mock tests affected by the code move, deleting a function which
>> indeed was not being used since commit 733b57f262b0("cxl/pci: Early
>> setup RCH dport component registers from RCRB").
>>
>> Signed-off-by: Alejandro Lucero <alucerop@....com>
>> Reviewed-by: Dave Jiang <dave.jiang@...el.com>
>> Reviewed-by: Ben Cheatham <benjamin.cheatham@....com>
>> Reviewed-by: Fan Ni <fan.ni@...sung.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
>> Reviewed-by: Alison Schofield <alison.schofield@...el.com>
>> Reviewed-by: Dan Williams <dan.j.williams@...el.com>
> [snip]
>
>> diff --git a/include/cxl/pci.h b/include/cxl/pci.h
>> index 5729a93b252a..d31e1363e1fd 100644
>> --- a/include/cxl/pci.h
>> +++ b/include/cxl/pci.h
>> @@ -4,6 +4,8 @@
>>   #ifndef __CXL_CXL_PCI_H__
>>   #define __CXL_CXL_PCI_H__
>>   
>> +#include <linux/pci.h>
>> +
> Unrelated change, it looks like this should be in the 1st patch.


Yes, you are right.

I'll fix it.


Thanks!


>
>>   /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
>>   #define CXL_DVSEC_PCIE_DEVICE					0
>>   #define   CXL_DVSEC_CAP_OFFSET		0xA