netdev - Re: [PATCH] dt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schema

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Message-ID: <87ms6di7sn.fsf@bootlin.com>
Date: Mon, 29 Sep 2025 17:43:04 +0200
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: "Rob Herring (Arm)" <robh@...nel.org>
Cc: Michael Turquette <mturquette@...libre.com>,  Stephen Boyd
 <sboyd@...nel.org>,  Krzysztof Kozlowski <krzk+dt@...nel.org>,  Conor
 Dooley <conor+dt@...nel.org>,  Linus Walleij <linus.walleij@...aro.org>,
  Richard Cochran <richardcochran@...il.com>,  Gregory CLEMENT
 <gregory.clement@...tlin.com>,  Marek Behún
 <kabel@...nel.org>,
  linux-clk@...r.kernel.org,  devicetree@...r.kernel.org,
  linux-kernel@...r.kernel.org,  linux-gpio@...r.kernel.org,
  netdev@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: pinctrl: Convert
 marvell,armada-3710-(sb|nb)-pinctrl to DT schema

On 24/09/2025 at 17:35:24 -05, "Rob Herring (Arm)" <robh@...nel.org> wrote:

> Convert the marvell,armada3710-(sb|nb)-pinctrl binding to DT schema
> format. The binding includes the "marvell,armada-3700-xtal-clock"
> subnode which is simple enough to include here.
>
> Signed-off-by: Rob Herring (Arm) <robh@...nel.org>
> ---
>  .../bindings/clock/armada3700-xtal-clock.txt  |  29 ---
>  .../marvell,armada-3710-xb-pinctrl.yaml       | 122 +++++++++++
>  .../pinctrl/marvell,armada-37xx-pinctrl.txt   | 195 ------------------
>  3 files changed, 122 insertions(+), 224 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-3710-xb-pinctrl.yaml
>  delete mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt b/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
> deleted file mode 100644
> index 4c0807f28cfa..000000000000
> --- a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -* Xtal Clock bindings for Marvell Armada 37xx SoCs
> -
> -Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
> -reading the gpio latch register.
> -
> -This node must be a subnode of the node exposing the register address
> -of the GPIO block where the gpio latch is located.
> -See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
> -
> -Required properties:
> -- compatible : shall be one of the following:
> -	"marvell,armada-3700-xtal-clock"
> -- #clock-cells : from common clock binding; shall be set to 0
> -
> -Optional properties:
> -- clock-output-names : from common clock binding; allows overwrite default clock
> -	output names ("xtal")
> -
> -Example:
> -pinctrl_nb: pinctrl-nb@...00 {
> -	compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
> -	reg = <0x13800 0x100>, <0x13C00 0x20>;
> -
> -	xtalclk: xtal-clk {
> -		compatible = "marvell,armada-3700-xtal-clock";
> -		clock-output-names = "xtal";
> -		#clock-cells = <0>;
> -	};
> -};
> diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-3710-xb-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,armada-3710-xb-pinctrl.yaml
> new file mode 100644
> index 000000000000..c4d09d8720bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-3710-xb-pinctrl.yaml
> @@ -0,0 +1,122 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/marvell,armada-3710-xb-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Marvell Armada 37xx SoC pin and gpio controller
> +
> +maintainers:
> +  - Gregory CLEMENT <gregory.clement@...tlin.com>
> +  - Marek Behún <kabel@...nel.org>
> +  - Miquel Raynal <miquel.raynal@...tlin.com>
> +
> +description: >
> +  Each Armada 37xx SoC come with two pin and gpio controller one for the south
> +  bridge and the other for the north bridge.

As I think you'll send a v2 because of the robot complaint, maybe you
could rephrase a bit to ease the reading:

"...two pin/gpio controllers, one for..."

> +
> +  Inside this set of register the gpio latch allows exposing some configuration
> +  of the SoC and especially the clock frequency of the xtal. Hence, this node is
> +  a represent as syscon allowing sharing the register between multiple hardware

represented as a?

> +  block.

blocks?


The rest looks fine, so:

Reviewed-by: Miquel Raynal <miquel.raynal@...tlin.com>

Thanks,
Miquèl