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Message-ID: <IA1PR11MB624194E104B1C5E71F747FBC8BE4A@IA1PR11MB6241.namprd11.prod.outlook.com>
Date: Fri, 3 Oct 2025 07:45:13 +0000
From: "Rinitha, SX" <sx.rinitha@...el.com>
To: "Nitka, Grzegorz" <grzegorz.nitka@...el.com>,
	"intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "Kolacinski, Karol"
	<karol.kolacinski@...el.com>, "Olech, Milena" <milena.olech@...el.com>,
	"Kitszel, Przemyslaw" <przemyslaw.kitszel@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH iwl-net v1] ice: fix lane number
 calculation

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of Grzegorz Nitka
> Sent: 21 February 2025 15:10
> To: intel-wired-lan@...ts.osuosl.org
> Cc: netdev@...r.kernel.org; Kolacinski, Karol <karol.kolacinski@...el.com>; Olech, Milena <milena.olech@...el.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@...el.com>
> Subject: [Intel-wired-lan] [PATCH iwl-net v1] ice: fix lane number calculation
>
> E82X adapters do not have sequential IDs, lane number is PF ID.
>
> Add check for ICE_MAC_GENERIC and skip checking port options.
>
> Also, adjust logical port number for specific E825 device with external PHY support (PCI device id 0x579F). For this particular device, with 2x25G (PHY0) and 2x10G (PHY1) port configuration, modification of pf_id -> lane_number mapping is required. PF IDs on the 2nd PHY start from 4 in such scenario. Otherwise, the lane number cannot be determined correctly, leading to PTP init errors during PF initialization.
>
> Fixes: 258f5f9058159 ("ice: Add correct PHY lane assignment")
> Co-developed-by: Karol Kolacinski <karol.kolacinski@...el.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@...el.com>
> Reviewed-by: Milena Olech <milena.olech@...el.com>
> ---
> drivers/net/ethernet/intel/ice/ice_common.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>

Tested-by: Rinitha S <sx.rinitha@...el.com> (A Contingent worker at Intel)

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