netdev - Re: [PATCH v19 11/22] cxl: Define a driver interface for HPA free space enumeration

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Message-ID: <7a3d3249-ee08-4fe0-a016-829ece6f7b8e@amd.com>
Date: Thu, 9 Oct 2025 15:55:51 -0500
From: "Cheatham, Benjamin" <benjamin.cheatham@....com>
To: <alejandro.lucero-palau@....com>
CC: Jonathan Cameron <Jonathan.Cameron@...wei.com>,
	<linux-cxl@...r.kernel.org>, <netdev@...r.kernel.org>,
	<dan.j.williams@...el.com>, <edward.cree@....com>, <davem@...emloft.net>,
	<kuba@...nel.org>, <pabeni@...hat.com>, <edumazet@...gle.com>,
	<dave.jiang@...el.com>
Subject: Re: [PATCH v19 11/22] cxl: Define a driver interface for HPA free
 space enumeration

On 10/6/2025 5:01 AM, alejandro.lucero-palau@....com wrote:
> From: Alejandro Lucero <alucerop@....com>
> 
> CXL region creation involves allocating capacity from Device Physical Address
> (DPA) and assigning it to decode a given Host Physical Address (HPA). Before
> determining how much DPA to allocate the amount of available HPA must be
> determined. Also, not all HPA is created equal, some HPA targets RAM, some
> targets PMEM, some is prepared for device-memory flows like HDM-D and HDM-DB,
> and some is HDM-H (host-only).
> 
> In order to support Type2 CXL devices, wrap all of those concerns into
> an API that retrieves a root decoder (platform CXL window) that fits the
> specified constraints and the capacity available for a new region.
> 
> Add a complementary function for releasing the reference to such root
> decoder.
> 
> Based on https://lore.kernel.org/linux-cxl/168592159290.1948938.13522227102445462976.stgit@dwillia2-xfh.jf.intel.com/
> 
> Signed-off-by: Alejandro Lucero <alucerop@....com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
> ---

Hey Alejandro,

I've been testing this on my setup and noticed a few issues when BIOS sets up the HDM decoders. It came down to 2 issues:
	1) Enabling "Specific Purpose Memory" added a Soft Reserve resource below the CXL window resource and broke
	this patch (more below)
	2) The endpoint decoder was already set up which broke DPA allocation and then CXL region creation (see my response
	to patch 18/22 for fix and explanation)

The fix I did for 1 is a bit hacky but it's essentially checking none of the resources below the CXL window are onlined as
system memory. It's roughly equivalent to what's being done in the CXL_PARTMODE_RAM case of cxl_region_probe(), but
I'm restricting the resources to "Soft Reserved" to be safe.

The diff for 2 is pretty big. If you don't want to take it at this point I can send it as a follow up. In that case I'd definitely
add that auto regions won't work in at least the cover letter (and in the description of 18/22 as well?).

---

diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index acaca64764bf..2d60131edff3 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -784,6 +784,19 @@ static int find_max_hpa(struct device *dev, void *data)
        lockdep_assert_held_read(&cxl_rwsem.region);
        res = cxlrd->res->child;

+       /*
+        * BIOS may have marked the CXL window as soft reserved. Make sure it's
+        * free to use.
+        */
+       while (res && resource_size(res) == resource_size(cxlrd->res)) {
+               if ((res->flags & IORESOURCE_BUSY) ||
+                   (res->flags & IORESOURCE_SYSRAM) ||
+                   strcmp(res->name, "Soft Reserved") != 0)
+                       return 0;
+
+               res = res->child;
+       }
+
        /* With no resource child the whole parent resource is available */
        if (!res)
                max = resource_size(cxlrd->res);