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Message-ID: <IA1PR11MB62410DD80696835C74F231688BEBA@IA1PR11MB6241.namprd11.prod.outlook.com>
Date: Tue, 14 Oct 2025 10:00:12 +0000
From: "Rinitha, SX" <sx.rinitha@...el.com>
To: "Nitka, Grzegorz" <grzegorz.nitka@...el.com>,
"intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "pmenzel@...gen.mpg.de" <pmenzel@...gen.mpg.de>, "netdev@...r.kernel.org"
<netdev@...r.kernel.org>, "Kubalewski, Arkadiusz"
<arkadiusz.kubalewski@...el.com>, "Loktionov, Aleksandr"
<aleksandr.loktionov@...el.com>, "Nguyen, Anthony L"
<anthony.l.nguyen@...el.com>, "Korba, Przemyslaw"
<przemyslaw.korba@...el.com>, "Olech, Milena" <milena.olech@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH v10 iwl-next] ice: add recovery clock
and clock 1588 control for E825c
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of Grzegorz Nitka
> Sent: 05 September 2025 20:40
> To: intel-wired-lan@...ts.osuosl.org
> Cc: pmenzel@...gen.mpg.de; netdev@...r.kernel.org; Kubalewski, Arkadiusz <arkadiusz.kubalewski@...el.com>; Loktionov, Aleksandr <aleksandr.loktionov@...el.com>; Nguyen, Anthony L <anthony.l.nguyen@...el.com>; Korba, Przemyslaw <przemyslaw.korba@...el.com>; Olech, Milena <milena.olech@...el.com>
> Subject: [Intel-wired-lan] [PATCH v10 iwl-next] ice: add recovery clock and clock 1588 control for E825c
>
> From: Przemyslaw Korba <przemyslaw.korba@...el.com>
>
> Add control for E825 input pins: phy clock recovery and clock 1588.
> E825 does not provide control over platform level DPLL but it provides control over PHY clock recovery, and PTP/timestamp driven inputs for platform level DPLL [1].
>
> Introduce a software controlled layer of abstraction to:
> - create a DPLL of type EEC for E825c,
> - create recovered clock pin for each PF, and control them through writing to registers,
> - create pin to control clock 1588 for PF0, and control it through writing to registers.
>
> Usage example:
> - to get EEC PLL info
> $ ynl --family dpll --dump device-get
> [{'clock-id': 0,
> 'id': 6,
> 'lock-status': 'locked',
> 'mode': 'manual',
> 'mode-supported': ['manual'],
> 'module-name': 'ice',
> 'type': 'eec'},
> ...
> ]
>
> - to get 1588 and rclk pins info
> (note: in the output below, pin id=31 is a representor for 1588 input, while pins 32..35 corresponds to PHY clock inputs to SyncE module) $ ynl --family dpll --dump pin-get
> [{'board-label': 'CLK_IN_0',
> 'capabilities': set(),
> 'clock-id': 0,
> 'id': 27,
> 'module-name': 'ice',
> 'parent-device': [{'direction': 'input',
> 'parent-id': 6,
> 'state': 'connected'}],
> 'phase-adjust-max': 0,
> 'phase-adjust-min': 0,
> 'type': 'mux'},
> {'board-label': 'CLK_IN_1',
> 'capabilities': set(),
> 'clock-id': 0,
> 'id': 28,
> 'module-name': 'ice',
> 'parent-device': [{'direction': 'input',
> 'parent-id': 6,
> 'state': 'connected'}],
> 'phase-adjust-max': 0,
> 'phase-adjust-min': 0,
> 'type': 'mux'},
> {'board-label': 'pin_1588',
> 'capabilities': {'state-can-change'},
> 'clock-id': 0,
> 'id': 31,
> 'module-name': 'ice',
> 'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
> {'parent-id': 28, 'state': 'disconnected'}],
> 'phase-adjust-max': 0,
> 'phase-adjust-min': 0,
> 'type': 'synce-eth-port'},
> {'capabilities': {'state-can-change'},
> 'clock-id': 0,
> 'id': 32,
> 'module-name': 'ice',
> 'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
> {'parent-id': 28, 'state': 'disconnected'}],
> 'phase-adjust-max': 0,
> 'phase-adjust-min': 0,
> 'type': 'synce-eth-port'},
> {'capabilities': {'state-can-change'},
> 'clock-id': 0,
> 'id': 33,
> 'module-name': 'ice',
> 'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
> {'parent-id': 28, 'state': 'disconnected'}],
> 'phase-adjust-max': 0,
> 'phase-adjust-min': 0,
> 'type': 'synce-eth-port'},
> {'capabilities': {'state-can-change'},
> 'clock-id': 0,
> 'id': 34,
> 'module-name': 'ice',
> 'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
> {'parent-id': 28, 'state': 'disconnected'}],
> 'phase-adjust-max': 0,
> 'phase-adjust-min': 0,
> 'type': 'synce-eth-port'},
> {'capabilities': {'state-can-change'},
> 'clock-id': 0,
> 'id': 35,
> 'module-name': 'ice',
> 'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
> {'parent-id': 28, 'state': 'disconnected'}],
> 'phase-adjust-max': 0,
> 'phase-adjust-min': 0,
> 'type': 'synce-eth-port'}]
>
> - to set PHY0 clock as SyncE module input $ ynl --family dpll --do pin-set --json '{"id":32,"parent-pin":\
> {"parent-id":27, "state":"connected"}}'
>
> - to set 1588 Main Timer as source into SyncE module $ ynl --family dpll --do pin-set --json '{"id":31,"parent-pin":\
> {"parent-id":27, "state":"connected"}}'
>
> [1] Granite Rapids D SAS - Timesync and SyncE
>
> Reviewed-by: Milena Olech <milena.olech@...el.com>
> Co-developed-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> Signed-off-by: Przemyslaw Korba <przemyslaw.korba@...el.com>
> ---
> v9->v10:
> - replaced SET_PIN_STATE with inline function
> - fixed wrong conflict resolution in ice_dpll_deinit_dpll()
> v8->v9:
> - rebased
> - moved ice_dpll_cfg_bypass_mux_e825c, ice_dpll_cfg_synce_ethdiv_e825c,
> ice_dpll_get_div_e825c to ice_tspll.c module
> - re-applying ts_pll settings on ptp status change (added
> ice_tspll_bypass_mux_active_e825c function)
> - improved doc strings
> - removed unrealted changes
> - renamed dpll to DPLL in doc strings where applicable
> v7->v8:
> - rebased
> - removed unrelated changes
> - change pin_1588 type to DPLL_PIN_TYPE_EXT
> - use ICE_SYNCE_CLK_NUM to determine the number of rclk pins
> ---
> drivers/net/ethernet/intel/ice/ice_dpll.c | 675 ++++++++++++++++++--
> drivers/net/ethernet/intel/ice/ice_dpll.h | 20 +
> drivers/net/ethernet/intel/ice/ice_lib.c | 3 +
> drivers/net/ethernet/intel/ice/ice_ptp.c | 29 +
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 34 +-
> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 1 +
> drivers/net/ethernet/intel/ice/ice_tspll.c | 223 +++++++ drivers/net/ethernet/intel/ice/ice_tspll.h | 14 +-
> drivers/net/ethernet/intel/ice/ice_type.h | 6 +
> 9 files changed, 945 insertions(+), 60 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@...el.com> (A Contingent worker at Intel)
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