netdev - RE: [Intel-wired-lan] [PATCH v3 iwl-next] ice: add TS PLL control for E825 devices

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Message-ID: <IA1PR11MB6241F6AD266AB7063CAE0AA98BE9A@IA1PR11MB6241.namprd11.prod.outlook.com>
Date: Thu, 16 Oct 2025 04:39:46 +0000
From: "Rinitha, SX" <sx.rinitha@...el.com>
To: "Nitka, Grzegorz" <grzegorz.nitka@...el.com>,
	"intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "Kubalewski, Arkadiusz"
	<arkadiusz.kubalewski@...el.com>, "pmenzel@...gen.mpg.de"
	<pmenzel@...gen.mpg.de>
Subject: RE: [Intel-wired-lan] [PATCH v3 iwl-next] ice: add TS PLL control for
 E825 devices

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of Grzegorz Nitka
> Sent: 26 September 2025 14:22
> To: intel-wired-lan@...ts.osuosl.org
> Cc: netdev@...r.kernel.org; Kubalewski, Arkadiusz <arkadiusz.kubalewski@...el.com>; pmenzel@...gen.mpg.de
> Subject: [Intel-wired-lan] [PATCH v3 iwl-next] ice: add TS PLL control for E825 devices
>
> Add ability to control CGU (Clock Generation Unit) 1588 Clock Reference mux selection for E825 devices. There are two clock sources available which might serve as input source to TSPLL block:
> - internal cristal oscillator (TXCO)
> - signal from external DPLL
>
> E825 does not provide control over platform level DPLL but it provides control over TIME_REF output from platform level DPLL.
> Introduce a software controlled layer of abstraction:
> - create a DPLL (referred as TSPLL DPLL) of PPS type for E825c,
> - define input pin for that DPLL to mock TIME_REF pin
> - define output pin for that DPLL to mock TIME_SYNC pin which supplies a
>  signal for master timer
>
> Note:
> - There is only one frequency supported (156.25 MHz) for TIME_REF
>  signal for E825 devices.
> - TIME_SYNC pin is always connected, as it supplies either internal TXCO
>  signal or a signal from external DPLL always
>
> Add kworker thread to track E825 TSPLL DPLL lock status. In case of lock status change, notify the user about the change, and try to lock it back (if lost). Lock status is checked every 500ms by default. The timer is decreased to 10ms in case of errors while accessing CGU registers.
> If error counter exceeds the threshold (50), the kworker thread is stopped and appropriate error message is displayed in dmesg log.
> Refactor the code by adding 'periodic_work' callback within ice_dplls structure to make the solution more generic and allow different type of devices to register their own callback.
>
> Usage example (ynl is a part of kernel's tools located under tools/net/ynl path):
> - to get TSPLL DPLL info
> $ ynl --family dpll --dump device-get
> ...
> {'clock-id': 0,
>  'id': 9,
>  'lock-status': 'locked',
>  'mode': 'manual',
>  'mode-supported': ['manual'],
>  'module-name': 'ice',
>  'type': 'pps'}]
> ...
>
> - to get TIMER_REF and TIME_SYNC pin info $ ynl --family dpll --dump pin-get ...
> {'board-label': 'TIME_REF',
>  'capabilities': {'state-can-change'},
>  'clock-id': 0,
>  'frequency': 156250000,
>  'frequency-supported': [{'frequency-max': 156250000,
>                           'frequency-min': 156250000}],
>  'id': 38,
>  'module-name': 'ice',
>  'parent-device': [{'direction': 'input',
>                     'parent-id': 9,
>                     'state': 'connected'}],
>  'phase-adjust-max': 0,
>  'phase-adjust-min': 0,
>  'type': 'ext'},
> {'board-label': 'TIME_SYNC',
>  'capabilities': set(),
>  'clock-id': 0,
>  'id': 39,
>  'module-name': 'ice',
>  'parent-device': [{'direction': 'output',
>                     'parent-id': 9,
>                     'state': 'connected'}],
>  'phase-adjust-max': 0,
>  'phase-adjust-min': 0,
>  'type': 'int-oscillator'},
> ...
>
> - to enable TIME_REF output
> $ ynl --family dpll --do pin-set --json '{"id":38,"parent-device":\ {"parent-id":9, "state":"connected"}}'
>
> - to disable TIME_REF output (TXCO is enabled) $ ynl --family dpll --do pin-set --json '{"id":38,"parent-device":\ {"parent-id":9, "state":"disconnected"}}'
>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> ---
> v2->v3:
> - replaced pf with hw struct as argument in ice_tspll_set_cfg
> - improved worker for TSPLL control (reworded dmesg log, use already
>  exist cgu state error counter to limit dmesg spamming, disable the
>  thread after error threshold is exceeded)
> - doc strings updateds (missing newly added pins description)
> - addresses comments from v2: use ternanry when applicable, commit
>  message typos
> - rebased
> v1->v2:
> - updated pin_type_name array with the names for newly added pin
>  types
> - added TS PLL lock status monitor
> ---
> drivers/net/ethernet/intel/ice/ice_dpll.c  | 384 +++++++++++++++++++--  drivers/net/ethernet/intel/ice/ice_dpll.h  |  12 +-  drivers/net/ethernet/intel/ice/ice_tspll.c | 122 +++++++
> drivers/net/ethernet/intel/ice/ice_tspll.h |   5 +
> 4 files changed, 499 insertions(+), 24 deletions(-)
>

Tested-by: Rinitha S <sx.rinitha@...el.com> (A Contingent worker at Intel)