netdev - Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

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Message-ID: <9280864d0eba182d06d1e191fdc0aad1fb4ce5b3.camel@collabora.com>
Date: Wed, 22 Oct 2025 08:56:06 +0200
From: Sjoerd Simons <sjoerd@...labora.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Eric Woudstra <ericwouds@...il.com>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski	 <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Matthias Brugger	 <matthias.bgg@...il.com>,
 AngeloGioacchino Del Regno	 <angelogioacchino.delregno@...labora.com>,
 Ryder Lee <ryder.lee@...iatek.com>,  Jianjun Wang
 <jianjun.wang@...iatek.com>, Bjorn Helgaas <bhelgaas@...gle.com>, Lorenzo
 Pieralisi	 <lpieralisi@...nel.org>, Krzysztof Wilczyński	
 <kwilczynski@...nel.org>, Manivannan Sadhasivam <mani@...nel.org>, Chunfeng
 Yun	 <chunfeng.yun@...iatek.com>, Vinod Koul <vkoul@...nel.org>, Kishon
 Vijay Abraham I <kishon@...nel.org>, Lee Jones <lee@...nel.org>, Andrew
 Lunn <andrew+netdev@...n.ch>,  "David S. Miller" <davem@...emloft.net>,
 Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo
 Abeni <pabeni@...hat.com>, Lorenzo Bianconi <lorenzo@...nel.org>, Felix
 Fietkau <nbd@....name>, 	kernel@...labora.com, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, 	linux-arm-kernel@...ts.infradead.org,
 linux-mediatek@...ts.infradead.org, 	linux-pci@...r.kernel.org,
 linux-phy@...ts.infradead.org, netdev@...r.kernel.org,  Daniel Golle
 <daniel@...rotopia.org>, Bryan Hinton <bryan@...anhinton.com>
Subject: Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable
 Ethernet

On Tue, 2025-10-21 at 22:40 +0200, Andrew Lunn wrote:
> On Tue, Oct 21, 2025 at 10:21:31PM +0200, Sjoerd Simons wrote:
> > On Fri, 2025-10-17 at 19:31 +0200, Andrew Lunn wrote:
> > > > +&mdio_bus {
> > > > +	phy15: ethernet-phy@f {
> > > > +		compatible = "ethernet-phy-id03a2.a411";
> > > > +		reg = <0xf>;
> > > > +		interrupt-parent = <&pio>;
> > > > +		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
> > > 
> > > This is probably wrong. PHY interrupts are generally level, not edge.
> > 
> > Sadly i can't find a datasheet for the PHY, so can't really validate that
> > easily.
> 
> What PHY is it? Look at the .handle_interrupt function in the
> driver. If the hardware supports a single interrupt bit, it could in
> theory support edge. However, as soon as you have multiple bits, you
> need level, to avoid races where an interrupt happens while you are
> clearing other interrupts.

ethernet-phy-id03a2.a411 is Airoha EN8811H (air_en8811h driver). Handle
interrupt there seems to just be a general interrupt clear followed by a
`phy_trigger_machine`. It doesn't seem to read specific interrupt status. 

Testing with IRQ_TYPE_LEVEL_LOW does seem to work as expected and results in
detecting 4 interrupts rather then just 1 with edges when enabling the
interface. However I'm not sure what can be concluded from that if anything :)..

I can stick a scope on the line in the coming days to see how the interrupt line
behaves if interrupts aren't cleared, which may clarify things.

-- 
Sjoerd Simons
Collabora