netdev - Re: [PATCH net-next v5 05/15] octeontx2-af: Add support for CPT second pass

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Message-ID:
 <IA2PR18MB58852FD7DD14B7E7F4FA7035D6FAA@IA2PR18MB5885.namprd18.prod.outlook.com>
Date: Wed, 29 Oct 2025 17:09:28 +0000
From: Tanmay Jagdale <tanmay@...vell.com>
To: Simon Horman <horms@...nel.org>
CC: "davem@...emloft.net" <davem@...emloft.net>,
        "leon@...nel.org"
	<leon@...nel.org>,
        "herbert@...dor.apana.org.au"
	<herbert@...dor.apana.org.au>,
        Bharat Bhushan <bbhushan2@...vell.com>,
        Sunil
 Kovvuri Goutham <sgoutham@...vell.com>,
        "linux-crypto@...r.kernel.org"
	<linux-crypto@...r.kernel.org>,
        "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>,
        Rakesh Kudurumalla <rkudurumalla@...vell.com>
Subject: Re: [PATCH net-next v5 05/15] octeontx2-af: Add support for CPT
 second pass

Hi Simon,

>> From: Rakesh Kudurumalla <rkudurumalla@...vell.com>
>> 
>> Implemented mailbox to add mechanism to allocate a
>> rq_mask and apply to nixlf to toggle RQ context fields
>> for CPT second pass packets.
>> 
>> Signed-off-by: Rakesh Kudurumalla <rkudurumalla@...vell.com>
>> Signed-off-by: Tanmay Jagdale <tanmay@...vell.com>
>
> ...
>
>> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
>> index c3d6f363bf61..95f93a29a00e 100644
>> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
>> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
>> @@ -6632,3 +6632,128 @@ void rvu_block_bcast_xon(struct rvu *rvu, int blkaddr)
>>  	cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(0));
>>  	rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(0), cfg);
>>  }
>> +
>> +static inline void
>> +configure_rq_mask(struct rvu *rvu, int blkaddr, int nixlf,
>> +		  u8 rq_mask, bool enable)
>
> Hi Rakesh and Tanmay,
>
> Please don't use inline in C files unless there is a demonstrable - usually
> performance - reason to do so.  Rather, please let the compiler inline code
> as it sees fit.
ACK. Will drop the inline in the next version.

>> +{
>> +	u64 cfg, reg;
>> +
>> +	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(nixlf));
>> +	reg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf));
>> +	if (enable) {
>> +		cfg |= NIX_AF_LFX_RX_IPSEC_CFG1_RQ_MASK_ENA;
>> +		reg &= ~NIX_AF_LFX_CFG_RQ_CPT_MASK_SEL;
>> +		reg |= FIELD_PREP(NIX_AF_LFX_CFG_RQ_CPT_MASK_SEL, rq_mask);
>> +	} else {
>> +		cfg &= ~NIX_AF_LFX_RX_IPSEC_CFG1_RQ_MASK_ENA;
>> +		reg &= ~NIX_AF_LFX_CFG_RQ_CPT_MASK_SEL;
>> +	}
>> +	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(nixlf), cfg);
>> +	rvu_write64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf), reg);
>> +}
>> +
>> +static inline void
>> +configure_spb_cpt(struct rvu *rvu, int blkaddr, int nixlf,
>> +		  struct nix_rq_cpt_field_mask_cfg_req *req, bool enable)
>
> Here too.
ACK.


>> +{
>> +	u64 cfg;
>> +
>> +	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(nixlf));
>> +
>> +	/* Clear the SPB bit fields */
>> +	cfg &= ~NIX_AF_LFX_RX_IPSEC_CFG1_SPB_CPT_ENA;
>> +	cfg &= ~NIX_AF_LFX_RX_IPSEC_CFG1_SPB_CPT_SZM1;
>> +	cfg &= ~NIX_AF_LFX_RX_IPSEC_CFG1_SPB_AURA;
>> +
>> +	if (enable) {
>> +		cfg |= NIX_AF_LFX_RX_IPSEC_CFG1_SPB_CPT_ENA;
>> +		cfg |= FIELD_PREP(NIX_AF_LFX_RX_IPSEC_CFG1_SPB_CPT_SZM1,
>> +				  req->ipsec_cfg1.spb_cpt_sizem1);
>> +		cfg |= FIELD_PREP(NIX_AF_LFX_RX_IPSEC_CFG1_SPB_AURA,
>> +				  req->ipsec_cfg1.spb_cpt_aura);
>> +	}
>> +
>> +	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(nixlf), cfg);
>> +}

Thanks,
Tanmay
...