netdev - Re: [PATCH net-next 2/2] net: phy: microchip_t1s: configure link status control for LAN867x Rev.D0

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Message-ID: <3ecf0e2a-37ea-4d2c-96a5-b83a03cc77c2@lunn.ch>
Date: Thu, 30 Oct 2025 15:53:47 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Parthiban Veerasooran <parthiban.veerasooran@...rochip.com>
Cc: hkallweit1@...il.com, linux@...linux.org.uk, davem@...emloft.net,
	edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next 2/2] net: phy: microchip_t1s: configure link
 status control for LAN867x Rev.D0

On Thu, Oct 30, 2025 at 03:52:58PM +0530, Parthiban Veerasooran wrote:
> Configure the link status in the Link Status Control register for
> LAN8670/1/2 Rev.D0 PHYs, depending on whether PLCA or CSMA/CD mode
> is enabled. When PLCA is enabled, the link status reflects the PLCA
> status. When PLCA is disabled (CSMA/CD mode), the PHY does not support
> autonegotiation, so the link status is forced active by setting
> the LINK_STATUS_SEMAPHORE bit.
> 
> The link status control is configured:
> - During PHY initialization, for default CSMA/CD mode.
> - Whenever PLCA configuration is updated.
> 
> This ensures correct link reporting and consistent behavior for
> LAN867x Rev.D0 devices.
> 
> Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@...rochip.com>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew