netdev - RE: [PATCH net-next 0/3] net: enetc: add port MDIO support for both i.MX94 and i.MX95

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Message-ID:
 <PAXPR04MB8510744BB954BB245FA7A4A088F8A@PAXPR04MB8510.eurprd04.prod.outlook.com>
Date: Fri, 31 Oct 2025 01:49:07 +0000
From: Wei Fang <wei.fang@....com>
To: Andrew Lunn <andrew@...n.ch>
CC: Claudiu Manoil <claudiu.manoil@....com>, Vladimir Oltean
	<vladimir.oltean@....com>, Clark Wang <xiaoning.wang@....com>,
	"andrew+netdev@...n.ch" <andrew+netdev@...n.ch>, "davem@...emloft.net"
	<davem@...emloft.net>, "edumazet@...gle.com" <edumazet@...gle.com>,
	"kuba@...nel.org" <kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	Aziz Sellami <aziz.sellami@....com>, "imx@...ts.linux.dev"
	<imx@...ts.linux.dev>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH net-next 0/3] net: enetc: add port MDIO support for both
 i.MX94 and i.MX95

> > Similar to the external MDIO registers, each ENETC has a set of internal
> > MDIO registers to access its on-die PHY (PCS), so internal MDIO support
> > is also added.
> 
> Any reason to not just hard code it to 0?
> What is the reset default?
> 

For internal MDIO interface, the PHY address is fixed and we do not
get the internal PHY address from the DT. The only part of this patch
set related to internal MDIO is changing the base of the IMDIO register.
See patch 3:

-       mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
+
+       if (is_enetc_rev1(pf->si))
+               mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
+       else
+               mdio_priv->mdio_base = ENETC4_PM_IMDIO_BASE;

> DT describes hardware, not configuration. So getting this from DT
> seems wrong.
> 

What we get from the DT is the external PHY address, just like the mdio
driver, this external PHY address based on the board, ENETC needs to
know its external PHY address so that its port MIDO can work properly.
So I do not think this is a configuration.