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Message-Id: <E1vFt4n-0000000Choy-0IeG@rmk-PC.armlinux.org.uk>
Date: Mon, 03 Nov 2025 11:50:21 +0000
From: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
To: Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Fabio Estevam <festevam@...il.com>,
imx@...ts.linux.dev,
Jakub Kicinski <kuba@...nel.org>,
Jan Petrous <jan.petrous@....nxp.com>,
linux-arm-kernel@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
netdev@...r.kernel.org,
Paolo Abeni <pabeni@...hat.com>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
s32@....com,
Sascha Hauer <s.hauer@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>
Subject: [PATCH net-next 06/11] net: stmmac: imx: convert to PHY_INTF_SEL_xxx
Convert dwmac-imx to use the PHY_INTF_SEL_xxx definitions rather than
constants via:
- ensuring that the prefix for the MASK and value definitions is the
same.
- using FIELD_PREP() to shift the PHY_INTF_SEL_xxx definition to the
appropriate bitfield.
Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-imx.c | 23 ++++++++++++-------
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
index 147fa08d5b6e..4fbee59e7337 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
@@ -23,18 +23,25 @@
#include "stmmac_platform.h"
#define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16)
-#define GPR_ENET_QOS_INTF_SEL_MII (0x0 << 16)
-#define GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 16)
-#define GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 16)
+#define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16)
+#define GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \
+ PHY_INTF_SEL_GMII_MII)
+#define GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \
+ PHY_INTF_SEL_RMII)
+#define GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \
+ PHY_INTF_SEL_RGMII)
#define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19)
#define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20)
#define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
#define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
-#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
-#define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
-#define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
-#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
+#define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1)
+#define MX93_GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \
+ PHY_INTF_SEL_GMII_MII)
+#define MX93_GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \
+ PHY_INTF_SEL_RMII)
+#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \
+ PHY_INTF_SEL_RGMII)
#define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
#define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0)
#define MX93_GPR_CLK_SEL_OFFSET (4)
@@ -241,7 +248,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
return;
- iface &= MX93_GPR_ENET_QOS_INTF_MASK;
+ iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK;
if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
return;
--
2.47.3
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