netdev - Re: [PATCH net-next v7 12/12] net: dsa: add driver for MaxLinear GSW1xx switch family

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Message-ID: <8f36e6218221bb9dad6aabe4989ee4fc279581ce.camel@siemens.com>
Date: Tue, 4 Nov 2025 08:03:07 +0000
From: "Sverdlin, Alexander" <alexander.sverdlin@...mens.com>
To: "daniel@...rotopia.org" <daniel@...rotopia.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
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	<olteanv@...il.com>, "robh@...nel.org" <robh@...nel.org>, "lxu@...linear.com"
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	"davem@...emloft.net" <davem@...emloft.net>, "yweng@...linear.com"
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Subject: Re: [PATCH net-next v7 12/12] net: dsa: add driver for MaxLinear
 GSW1xx switch family

Hi Daniel,

On Mon, 2025-11-03 at 12:20 +0000, Daniel Golle wrote:
> Add driver for the MaxLinear GSW1xx family of Ethernet switch ICs which
> are based on the same IP as the Lantiq/Intel GSWIP found in the Lantiq VR9
> and Intel GRX MIPS router SoCs. The main difference is that instead of
> using memory-mapped I/O to communicate with the host CPU these ICs are
> connected via MDIO (or SPI, which isn't supported by this driver).
> Implement the regmap API to access the switch registers over MDIO to allow
> reusing lantiq_gswip_common for all core functionality.
> 
> The GSW1xx also comes with a SerDes port capable of 1000Base-X, SGMII and
> 2500Base-X, which can either be used to connect an external PHY or SFP
> cage, or as the CPU port. Support for the SerDes interface is implemented
> in this driver using the phylink_pcs interface.
> 
> Signed-off-by: Daniel Golle <daniel@...rotopia.org>

thank you for the patch!

Finally I was able to run selftest/drivers/net/dsa/local_termination.sh
with only 2 unexpected failures on a GSW145 hardware (with TI AM62
host CPU and its CPSW (not in switchdev mode) as CPU interface).

The problems I had in the past were neither related to the GSW145 code,
nor to am65-cpsw-nuss, but to the test itself:
https://lore.kernel.org/all/20251104061723.483301-1-alexander.sverdlin@siemens.com/

The remaining failing test cases are:
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address   [FAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti   [FAIL]
        reception succeeded, but should have failed

So far I didn't notice any problems with untagged read-word IP traffic over
GSW145 ports.

Do you have a suggestion what could I check further regarding the failing
test cases? As I understood, all of them pass on your side?

> ---
> v7: no changes
> 
> v6: no changes
> 
> v5: no changes
> 
> v4:
>  * break out PCS reset into dedicated function
>  * drop hacky support for reverse-SGMII
>  * remove again the custom properties for TX and RX inverted SerDes
>    PCS in favor of waiting for generic properties to land
> 
> v3:
>  * avoid disrupting link when calling .pcs_config()
>  * sort functions and phylink_pcs_ops instance in same order as
>    struct definition
>  * always set bootstrap override bits and add explanatory comment
>  * move definitions to separate header file
>  * add custom properties for TX and RX inverted data on the SerDes
>    interface
> 
> v2: remove left-overs of 4k VLAN support (will be added in future)
> 
> since RFC: no changes
> 
>  drivers/net/dsa/lantiq/Kconfig          |  12 +
>  drivers/net/dsa/lantiq/Makefile         |   1 +
>  drivers/net/dsa/lantiq/lantiq_gswip.h   |   1 +
>  drivers/net/dsa/lantiq/mxl-gsw1xx.c     | 733 ++++++++++++++++++++++++
>  drivers/net/dsa/lantiq/mxl-gsw1xx.h     | 126 ++++
>  drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h | 154 +++++
>  6 files changed, 1027 insertions(+)
>  create mode 100644 drivers/net/dsa/lantiq/mxl-gsw1xx.c
>  create mode 100644 drivers/net/dsa/lantiq/mxl-gsw1xx.h
>  create mode 100644 drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h

-- 
Alexander Sverdlin
Siemens AG
www.siemens.com