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Message-ID: <168cefb5-4a44-4836-8e55-c9c76e99f2aa@bootlin.com>
Date: Thu, 6 Nov 2025 11:20:03 +0100
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, linux-arm-kernel@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com,
Maxime Coquelin <mcoquelin.stm32@...il.com>, netdev@...r.kernel.org,
Paolo Abeni <pabeni@...hat.com>
Subject: Re: [PATCH net-next v2 09/11] net: stmmac: ingenic: simplify x2000
mac_set_mode()
On 06/11/2025 09:58, Russell King (Oracle) wrote:
> As per the previous commit, we have validated that the phy_intf_sel
> value is one that is permissible for this SoC, so there is no need to
> handle invalid PHY interface modes. We can also apply the other
> configuration based upon the phy_intf_sel value rather than the
> PHY interface mode.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
Reviewed-by: Maxime Chevallier <maxime.chevallier@...tlin.com>
Maxime
> ---
> .../ethernet/stmicro/stmmac/dwmac-ingenic.c | 28 +++++--------------
> 1 file changed, 7 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c
> index 7b2576fbb1e1..eb5744e0b9ea 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c
> @@ -122,39 +122,25 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat,
> struct ingenic_mac *mac = plat_dat->bsp_priv;
> unsigned int val;
>
> - switch (plat_dat->phy_interface) {
> - case PHY_INTERFACE_MODE_RMII:
> - val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
> - FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
> - break;
> -
> - case PHY_INTERFACE_MODE_RGMII:
> - case PHY_INTERFACE_MODE_RGMII_ID:
> - case PHY_INTERFACE_MODE_RGMII_TXID:
> - case PHY_INTERFACE_MODE_RGMII_RXID:
> - val = 0;
> + val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
> +
> + if (phy_intf_sel == PHY_INTF_SEL_RMII) {
> + val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
> + FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
> + } else if (phy_intf_sel == PHY_INTF_SEL_RGMII) {
> if (mac->tx_delay == 0)
> val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN);
> else
> val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_DELAY) |
> - FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1);
> + FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1);
>
> if (mac->rx_delay == 0)
> val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
> else
> val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_DELAY) |
> FIELD_PREP(MACPHYC_RX_DELAY_MASK, (mac->rx_delay + 9750) / 19500 - 1);
> -
> - break;
> -
> - default:
> - dev_err(mac->dev, "Unsupported interface %s\n",
> - phy_modes(plat_dat->phy_interface));
> - return -EINVAL;
> }
>
> - val |= FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
> -
> /* Update MAC PHY control register */
> return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
> }
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