netdev - Re: [PATCH iwl-next v2 2/9] ice: use cacheline groups for ice_rx

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Message-ID: <3e32abe4-5c7f-4cbf-b4de-1c136b921a95@intel.com>
Date: Thu, 6 Nov 2025 13:32:35 -0800
From: Jacob Keller <jacob.e.keller@...el.com>
To: Simon Horman <horms@...nel.org>
CC: Aleksandr Loktionov <aleksandr.loktionov@...el.com>, Alexander Lobakin
	<aleksander.lobakin@...el.com>, Tony Nguyen <anthony.l.nguyen@...el.com>,
	Przemek Kitszel <przemyslaw.kitszel@...el.com>,
	<intel-wired-lan@...ts.osuosl.org>, <netdev@...r.kernel.org>
Subject: Re: [PATCH iwl-next v2 2/9] ice: use cacheline groups for ice_rx_ring
 structure



On 11/6/2025 9:23 AM, Simon Horman wrote:
>> diff --git a/drivers/net/ethernet/intel/ice/ice_txrx.h b/drivers/net/ethernet/intel/ice/ice_txrx.h
>> @@ -298,10 +302,22 @@ struct ice_rx_ring {
>>  #define ICE_RX_FLAGS_MULTIDEV		BIT(3)
>>  #define ICE_RX_FLAGS_RING_GCS		BIT(4)
>>  	u8 flags;
>> -	/* CL5 - 5th cacheline starts here */
>> +	__cacheline_group_end_aligned(cl4);
>> +
>> +	__cacheline_group_begin_aligned(cl5);
>>  	struct xdp_rxq_info xdp_rxq;
>> +	__cacheline_group_end_aligned(cl5);
>>  } ____cacheline_internodealigned_in_smp;
>>  
>> +static inline void ice_rx_ring_struct_check(void)
>> +{
>> +	CACHELINE_ASSERT_GROUP_SIZE(struct ice_rx_ring, cl1, 64);
>> +	CACHELINE_ASSERT_GROUP_SIZE(struct ice_rx_ring, cl2, 64);
>> +	CACHELINE_ASSERT_GROUP_SIZE(struct ice_rx_ring, cl3, 64);
>> +	CACHELINE_ASSERT_GROUP_SIZE(struct ice_rx_ring, cl4, 64);
>> +	CACHELINE_ASSERT_GROUP_SIZE(struct ice_rx_ring, cl5, 64);
> 
> Hi Jacob,
> 
> Unfortunately the last line results in a build failure on ARM (32-bit)
> with allmodconfig. It seems that in that case the size of the group is
> 128 bytes.
> 

Hm. That's interesting. My understanding is that
CACHELINE_ASSERT_GROUP_SIZE calculates the size without taking into
account the padding after the last element added by the
cacheline_group_end_aligned. Perhaps there's something in one of the
groups that gets larger due to also being cacheline_aligned and ARM
system having 128-byte cacheline instead of 64, and thats what results
in the larger increase in size.

Is there an easy way to cross compile for ARM so I can check the struct
layout myself?

The easy fix option would be to only enable these assertions on the x86
platform they were designed for specifically.. But thats kind of ugly
and I don't like it...

>> +}
>> +
>>  struct ice_tx_ring {
>>  	/* CL1 - 1st cacheline starts here */
>>  	struct ice_tx_ring *next;	/* pointer to next ring in q_vector */
> 
> ...



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