netdev - [PATCH net-next 07/16] net: stmmac: meson8b: use PHY_INTF_SEL

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Message-Id: <E1vHNS6-0000000DkSV-39Ff@rmk-PC.armlinux.org.uk>
Date: Fri, 07 Nov 2025 14:28:34 +0000
From: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
To: Andrew Lunn <andrew@...n.ch>,
	Heiner Kallweit <hkallweit1@...il.com>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
	Andrew Lunn <andrew+netdev@...n.ch>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	"David S. Miller" <davem@...emloft.net>,
	Emil Renner Berthing <kernel@...il.dk>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>,
	Jerome Brunet <jbrunet@...libre.com>,
	Keguang Zhang <keguang.zhang@...il.com>,
	Kevin Hilman <khilman@...libre.com>,
	linux-amlogic@...ts.infradead.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-mediatek@...ts.infradead.org,
	linux-mips@...r.kernel.org,
	linux-stm32@...md-mailman.stormreply.com,
	Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
	Matthias Brugger <matthias.bgg@...il.com>,
	Maxime Coquelin <mcoquelin.stm32@...il.com>,
	Minda Chen <minda.chen@...rfivetech.com>,
	Neil Armstrong <neil.armstrong@...aro.org>,
	netdev@...r.kernel.org,
	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@...l.toshiba>,
	Paolo Abeni <pabeni@...hat.com>
Subject: [PATCH net-next 07/16] net: stmmac: meson8b: use PHY_INTF_SEL_xxx

Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index a50782994b97..f485b9b858bf 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -26,8 +26,8 @@
 #define PRG_ETH0_RGMII_MODE		BIT(0)
 
 #define PRG_ETH0_EXT_PHY_MODE_MASK	GENMASK(2, 0)
-#define PRG_ETH0_EXT_RGMII_MODE		1
-#define PRG_ETH0_EXT_RMII_MODE		4
+#define PRG_ETH0_EXT_RGMII_MODE		PHY_INTF_SEL_RGMII
+#define PRG_ETH0_EXT_RMII_MODE		PHY_INTF_SEL_RMII
 
 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
 #define PRG_ETH0_CLK_M250_SEL_MASK	GENMASK(4, 4)
-- 
2.47.3