netdev - Re: [PATCH net-next v2 04/13] net: stmmac: mediatek: use PHY_INTF_SEL

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Message-ID: <4d203e8d-64ba-4b08-9152-a059426a8a79@bootlin.com>
Date: Wed, 12 Nov 2025 16:48:45 +0100
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
 Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
 Andrew Lunn <andrew+netdev@...n.ch>,
 AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
 "David S. Miller" <davem@...emloft.net>,
 Emil Renner Berthing <kernel@...il.dk>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Keguang Zhang <keguang.zhang@...il.com>,
 linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
 linux-mips@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com,
 Matthias Brugger <matthias.bgg@...il.com>,
 Maxime Coquelin <mcoquelin.stm32@...il.com>,
 Minda Chen <minda.chen@...rfivetech.com>, netdev@...r.kernel.org,
 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@...l.toshiba>,
 Paolo Abeni <pabeni@...hat.com>
Subject: Re: [PATCH net-next v2 04/13] net: stmmac: mediatek: use
 PHY_INTF_SEL_x



On 11/11/2025 09:12, Russell King (Oracle) wrote:
> Use PHY_INTF_SEL_x definitions for the fields that correspond to the
> phy_intf_sel inputs to the dwmac core.
> 
> Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>

Reviewed-by: Maxime Chevallier <maxime.chevallier@...tlin.com>

Maxime

> ---
>  .../ethernet/stmicro/stmmac/dwmac-mediatek.c   | 18 ++++++++----------
>  1 file changed, 8 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> index f1b36f0a401d..dcdf28418fec 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> @@ -17,9 +17,6 @@
>  
>  /* Peri Configuration register for mt2712 */
>  #define PERI_ETH_PHY_INTF_SEL	0x418
> -#define PHY_INTF_MII		0
> -#define PHY_INTF_RGMII		1
> -#define PHY_INTF_RMII		4
>  #define RMII_CLK_SRC_RXC	BIT(4)
>  #define RMII_CLK_SRC_INTERNAL	BIT(5)
>  
> @@ -118,16 +115,16 @@ static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
>  	/* select phy interface in top control domain */
>  	switch (plat->phy_mode) {
>  	case PHY_INTERFACE_MODE_MII:
> -		intf_val |= PHY_INTF_MII;
> +		intf_val |= PHY_INTF_SEL_GMII_MII;
>  		break;
>  	case PHY_INTERFACE_MODE_RMII:
> -		intf_val |= (PHY_INTF_RMII | rmii_rxc | rmii_clk_from_mac);
> +		intf_val |= PHY_INTF_SEL_RMII | rmii_rxc | rmii_clk_from_mac;
>  		break;
>  	case PHY_INTERFACE_MODE_RGMII:
>  	case PHY_INTERFACE_MODE_RGMII_TXID:
>  	case PHY_INTERFACE_MODE_RGMII_RXID:
>  	case PHY_INTERFACE_MODE_RGMII_ID:
> -		intf_val |= PHY_INTF_RGMII;
> +		intf_val |= PHY_INTF_SEL_RGMII;
>  		break;
>  	default:
>  		dev_err(plat->dev, "phy interface not supported\n");
> @@ -297,17 +294,18 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat)
>  	/* select phy interface in top control domain */
>  	switch (plat->phy_mode) {
>  	case PHY_INTERFACE_MODE_MII:
> -		intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_MII);
> +		intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL,
> +				       PHY_INTF_SEL_GMII_MII);
>  		break;
>  	case PHY_INTERFACE_MODE_RMII:
> -		intf_val |= (rmii_rxc | rmii_clk_from_mac);
> -		intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RMII);
> +		intf_val |= rmii_rxc | rmii_clk_from_mac;
> +		intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_SEL_RMII);
>  		break;
>  	case PHY_INTERFACE_MODE_RGMII:
>  	case PHY_INTERFACE_MODE_RGMII_TXID:
>  	case PHY_INTERFACE_MODE_RGMII_RXID:
>  	case PHY_INTERFACE_MODE_RGMII_ID:
> -		intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RGMII);
> +		intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_SEL_RGMII);
>  		break;
>  	default:
>  		dev_err(plat->dev, "phy interface not supported\n");