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Message-ID:
<176305128544.3573217.7529629511881918177.stgit@ahduyck-xeon-server.home.arpa>
Date: Thu, 13 Nov 2025 08:32:56 -0800
From: Alexander Duyck <alexander.duyck@...il.com>
To: netdev@...r.kernel.org
Cc: kuba@...nel.org, kernel-team@...a.com, andrew+netdev@...n.ch,
hkallweit1@...il.com, linux@...linux.org.uk, pabeni@...hat.com,
davem@...emloft.net
Subject: [net-next PATCH v4 00/10] net: phy: Add support for fbnic PHY w/ 25G,
50G, and 100G support
To transition the fbnic driver to using the XPCS driver we need to address
the fact that we need a representation for the FW managed PMA/PMD that is
actually a SerDes PHY to handle link bouncing during link training.
This patch set first introduces the necessary bits to the
generic c45 driver code to enable it to read 25G, 50G, and 100G modes from
the PHY. After that we update the XPCS driver to to do the same.
The rest of this patch set enables the changes to fbnic to make use of these
interfaces and expose a PMA/PMD that can provide a necessary link delay to
avoid link flapping in the event that a cable is disconnected and
reconnected, and to correctly provide the count for the link down events.
With this we have the basic groundwork laid as with this all the bits and
pieces are in place in terms of reading the configuration. The general plan for
follow-on patch sets is to start looking at enabling changing the configuration
in environments where that is supported.
v2: Added XPCS code to the patch set
Dropped code adding bits for extended ability registers
Switched from enabling code in generic c45 to enabling code in fbnic_phy.c
Fixed several bugs related to phy state machine and use of resume
Moved PHY assignment into ndo_init/uninit
Renamed fbnic_swmii.c to fbnic_mdio.c
v3: Modified XPCS to have it read link from PMA instead of using a phydev
Fixed naming for PCS vs PMA for CTRL1 register speed bit values
Added logic to XPCS to get speed from PCS CTRL1 register
Swapped fbnic link delay timer from tracking training start to end
Dropped driver code for fbnic_phy.c and phydev code from patches
Updated patch naming to match expectations for PCS changes
Cleaned up dead code and defines from earlier versions
v4: Added back in UAPI defines for MDIO_CTRL1_SPEED[5G|2_5G] w/ comment
Swapped patches 1 and 2 placing the 2.5/5G fixes first
---
Alexander Duyck (10):
net: phy: Rename MDIO_CTRL1_SPEED for 2.5G and 5G to reflect PMA values
net: phy: Add support for 25, 50 and 100Gbps PMA to genphy_c45_read_pma
net: pcs: xpcs: Add support for 25G, 50G, and 100G interfaces
net: pcs: xpcs: Fix PMA identifier handling in XPCS
net: pcs: xpcs: Add support for FBNIC 25G, 50G, 100G PMA
fbnic: Rename PCS IRQ to MAC IRQ as it is actually a MAC interrupt
fbnic: Add logic to track PMD state via MAC/PCS signals
fbnic: Cleanup handling for link down event statistics
fbnic: Add SW shim for MDIO interface to PMA/PMD and PCS
fbnic: Replace use of internal PCS w/ Designware XPCS
drivers/net/ethernet/meta/Kconfig | 1 +
drivers/net/ethernet/meta/fbnic/Makefile | 1 +
drivers/net/ethernet/meta/fbnic/fbnic.h | 15 +-
drivers/net/ethernet/meta/fbnic/fbnic_csr.h | 2 +
.../net/ethernet/meta/fbnic/fbnic_ethtool.c | 9 +
drivers/net/ethernet/meta/fbnic/fbnic_irq.c | 45 +++--
drivers/net/ethernet/meta/fbnic/fbnic_mac.c | 71 ++++---
drivers/net/ethernet/meta/fbnic/fbnic_mac.h | 40 +++-
drivers/net/ethernet/meta/fbnic/fbnic_mdio.c | 190 ++++++++++++++++++
.../net/ethernet/meta/fbnic/fbnic_netdev.c | 11 +-
.../net/ethernet/meta/fbnic/fbnic_netdev.h | 6 +-
drivers/net/ethernet/meta/fbnic/fbnic_pci.c | 17 +-
.../net/ethernet/meta/fbnic/fbnic_phylink.c | 163 ++++++++-------
drivers/net/pcs/pcs-xpcs.c | 135 ++++++++++++-
drivers/net/phy/phy-c45.c | 17 +-
include/linux/pcs/pcs-xpcs.h | 4 +-
include/uapi/linux/mdio.h | 26 ++-
17 files changed, 600 insertions(+), 153 deletions(-)
create mode 100644 drivers/net/ethernet/meta/fbnic/fbnic_mdio.c
--
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