netdev - Re: LAN8720: RX errors / packet loss when using smsc PHY driver on i.MX6Q

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Message-ID: <aRjytF103DHLnmEQ@shell.armlinux.org.uk>
Date: Sat, 15 Nov 2025 21:37:56 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Fabio Estevam <festevam@...il.com>
Cc: Heiner Kallweit <hkallweit1@...il.com>, edumazet <edumazet@...gle.com>,
	netdev <netdev@...r.kernel.org>, Andrew Lunn <andrew@...n.ch>
Subject: Re: LAN8720: RX errors / packet loss when using smsc PHY driver on
 i.MX6Q

On Sat, Nov 15, 2025 at 06:01:38PM -0300, Fabio Estevam wrote:
> Hi Heiner,
> 
> On Fri, Nov 14, 2025 at 6:33 PM Heiner Kallweit <hkallweit1@...il.com> wrote:
> 
> > The smsc PHY driver for LAN8720 has a number of callbacks and flags.
> > Try commenting them out one after the other until it works.
> >
> > .read_status    = lan87xx_read_status,
> > .config_init    = smsc_phy_config_init,
> > .soft_reset     = smsc_phy_reset,
> > .config_aneg    = lan95xx_config_aneg_ext,
> > .suspend        = genphy_suspend,
> > .resume         = genphy_resume,
> > .flags          = PHY_RST_AFTER_CLK_EN,
> >
> > All of them are optional. If all are commented out, you should have
> > the behavior of the genphy driver.
> >
> > Once we know which callback is problematic, we have a starting point.
> 
> Thanks for the suggestion.
> 
> After removing the '.soft_reset = smsc_phy_reset,' line, there is no
> packet loss anymore.
> 
> If you have any other suggestions regarding smsc_phy_reset(), please
> let me know.

What happens if you replace this with genphy_soft_reset() ?

Is the hardware reset signal wired on this PHY, and does the kernel
control the hardware reset?

I note that phy_init_hw() will deassert the hardware reset, and with
.soft_reset populated, we will immediately thump the PHY with a
soft reset unless a reset_deassert_delay is specified (e.g. via DT
reset-deassert-us prioerty). This is probably not a good idea if the
PHY is still recovering from hardware reset.

For reference, LAN8720 requires a minimum period of 100µs for hardware
reset assertion, and then between 2 and 800ns before the PHY starts
driving the configuration pin outputs. This _probably_ (it's not
specified) means we shouldn't be talking to the PHY for approx. the
first 1µs.

Finally, and this is probably not relevant given that the PHY works
with the genphy driver, the PHY requires the XTAL1/CLKIN to be running
during a hardware reset.

This is from https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/LAN8720A-LAN8720Ai-Data-Sheet-DS00002165.pdf

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