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Message-ID: <CAOMZO5C49MudQzPzWuChyzBoemgZFCVBp9A1XPpCOcWNfDb0jg@mail.gmail.com>
Date: Sat, 15 Nov 2025 19:25:32 -0300
From: Fabio Estevam <festevam@...il.com>
To: "Russell King (Oracle)" <linux@...linux.org.uk>
Cc: Heiner Kallweit <hkallweit1@...il.com>, edumazet <edumazet@...gle.com>,
netdev <netdev@...r.kernel.org>, Andrew Lunn <andrew@...n.ch>
Subject: Re: LAN8720: RX errors / packet loss when using smsc PHY driver on i.MX6Q
On Sat, Nov 15, 2025 at 7:01 PM Russell King (Oracle)
<linux@...linux.org.uk> wrote:
> This is no proof. The two are not independent. See 3.7.2 of the LAN8720
> datasheet. A change to the MODE[2:0] field requires a soft reset to
> take effect.
>
> Avoiding the soft reset just means effectively you've disabled the
> effect of the write to MII_LAN83C185_SPECIAL_MODES. I don't see
> anywhere else that the driver would set the RESET bit in BMCR, so
> this write will never take effect.
On this board, MODE[2:0] is 111 , which comes from the strap MODE pins.
This means that the "If the SMSC PHY is in power down mode" path is
never executed on this board.
In the section you pointed out:
"Power Down mode. In this mode the transceiver will
wake-up in Power-Down mode. The transceiver
cannot be used when the MODE[2:0] bits are set to
this mode. To exit this mode, the MODE bits in Reg-
ister 18.7:5(see Section 4.2.9, "Special Modes Reg-
ister," on page 50) must be configured to some
other value and a soft reset must be issued."
I am wondering if the genphy_soft_reset() should happen only when if
the write to MII_LAN83C185_SPECIAL_MODES is done:
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -147,10 +147,10 @@ static int smsc_phy_reset(struct phy_device *phydev)
/* set "all capable" mode */
rc |= MII_LAN83C185_MODE_ALL;
phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc);
+ return genphy_soft_reset(phydev);
}
- /* reset the phy */
- return genphy_soft_reset(phydev);
+ return 0;
}
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