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Message-ID: <20251121113553.2955854-11-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Fri, 21 Nov 2025 11:35:36 +0000
From: Prabhakar <prabhakar.csengg@...il.com>
To: Clément Léger <clement.leger@...tlin.com>,
Andrew Lunn <andrew@...n.ch>,
Vladimir Oltean <olteanv@...il.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Simon Horman <horms@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Russell King <linux@...linux.org.uk>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>
Cc: linux-renesas-soc@...r.kernel.org,
netdev@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH net-next 10/11] net: dsa: rzn1-a5psw: Add support for RZ/T2H Ethernet switch
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Add device tree match data and configuration for the Renesas RZ/T2H
SoC Ethernet switch. The RZ/T2H uses the same A5PSW switch IP as RZ/N1
but with four ports, the DSA tagging protocol `DSA_TAG_PROTO_RZT2H_ETHSW`,
and an additional 8-byte management port frame length adjustment.
This prepares the driver to handle RZ/T2H and compatible RZ/N2H
Ethernet switch instances.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
drivers/net/dsa/rzn1_a5psw.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/net/dsa/rzn1_a5psw.c b/drivers/net/dsa/rzn1_a5psw.c
index 82f4236a726e..9f85a4526bd2 100644
--- a/drivers/net/dsa/rzn1_a5psw.c
+++ b/drivers/net/dsa/rzn1_a5psw.c
@@ -1319,6 +1319,13 @@ static void a5psw_shutdown(struct platform_device *pdev)
platform_set_drvdata(pdev, NULL);
}
+static const struct a5psw_of_data rzt2h_of_data = {
+ .nports = 4,
+ .cpu_port = 3,
+ .tag_proto = DSA_TAG_PROTO_RZT2H_ETHSW,
+ .management_port_frame_len_adj = 40,
+};
+
static const struct a5psw_of_data rzn1_of_data = {
.nports = 5,
.cpu_port = 4,
@@ -1326,6 +1333,7 @@ static const struct a5psw_of_data rzn1_of_data = {
};
static const struct of_device_id a5psw_of_mtable[] = {
+ { .compatible = "renesas,r9a09g077-ethsw", .data = &rzt2h_of_data },
{ .compatible = "renesas,rzn1-a5psw", .data = &rzn1_of_data },
{ /* sentinel */ },
};
--
2.52.0
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