netdev - Re: [PATCH net-next v2] octeon_ep: reset firmware ready status

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Message-ID: <aTRGrorVdpRfmWtd@horms.kernel.org>
Date: Sat, 6 Dec 2025 15:07:26 +0000
From: Simon Horman <horms@...nel.org>
To: Vimlesh Kumar <vimleshk@...vell.com>
Cc: netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
	sedara@...vell.com, srasheed@...vell.com, hgani@...vell.com,
	Veerasenareddy Burru <vburru@...vell.com>,
	Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>
Subject: Re: [PATCH net-next v2] octeon_ep: reset firmware ready status

On Fri, Dec 05, 2025 at 09:10:44AM +0000, Vimlesh Kumar wrote:
> Add support to reset firmware ready status
> when the driver is removed(either in unload
> or unbind)
> 
> Signed-off-by: Sathesh Edara <sedara@...vell.com>
> Signed-off-by: Shinas Rasheed <srasheed@...vell.com>
> Signed-off-by: Vimlesh Kumar <vimleshk@...vell.com>
> ---
> V2: Use recommended bit manipulation macros.

...

> diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
> index ca473502d7a0..284959d97ad1 100644
> --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
> +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
> @@ -383,6 +383,22 @@
>  /* bit 1 for firmware heartbeat interrupt */
>  #define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT	BIT_ULL(1)
>  
> +#define FW_STATUS_DOWNING      0ULL
> +#define FW_STATUS_RUNNING      2ULL
> +
> +#define CN9K_PEM_GENMASK BIT_ULL(36)
> +#define CN9K_PF_GENMASK GENMASK_ULL(21, 18)
> +#define PFX_CSX_PFCFGX_SHADOW_BIT BIT_ULL(16)
> +#define CN9K_PEMX_PFX_CSX_PFCFGX(pem, pf, offset)   ((0x8e0000008000 | (uint64_t)\
> +						      FIELD_PREP(CN9K_PEM_GENMASK, pem)\
> +						      | FIELD_PREP(CN9K_PF_GENMASK, pf)\
> +						      | (PFX_CSX_PFCFGX_SHADOW_BIT & (offset))\
> +						      | (rounddown((offset), 8)))\
> +						      + ((offset) & BIT_ULL(2)))

Hi Vimlesh,

Please use a #defines so that 0x8e0000008000 and for BIT_ULL(2) have names.

And please reformat so this is less than 80 columns wide.
I'd do something like this:

define CN9K_PEMX_PFX_CSX_PFCFGX(pem, pf, offset) \
	... \
	...

> +
> +/* Register defines for use with CN9K_PEMX_PFX_CSX_PFCFGX */
> +#define CN9K_PCIEEP_VSECST_CTL  0x4D0
> +
>  #define CN93_PEM_BAR4_INDEX            7
>  #define CN93_PEM_BAR4_INDEX_SIZE       0x400000ULL
>  #define CN93_PEM_BAR4_INDEX_OFFSET     (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE)

## Form letter - net-next-closed

The merge window for v6.19 has begun and therefore net-next has closed
for new drivers, features, code refactoring and optimizations. We are
currently accepting bug fixes only.

Please repost when net-next reopens.

Due to a combination of the merge-window, travel commitments of the
maintainers, and the holiday season, net-next will re-open after
2nd January.

RFC patches sent for review only are welcome at any time.

See: https://www.kernel.org/doc/html/next/process/maintainer-netdev.html#development-cycle

-- 
pw-bot: changes-requested