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Message-ID: <20251219-venomous-ninja-uakari-bf8d1a@quoll>
Date: Fri, 19 Dec 2025 08:35:04 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: "irving.ch.lin" <irving-ch.lin@...iatek.com>
Cc: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>, Ulf Hansson <ulf.hansson@...aro.org>,
Richard Cochran <richardcochran@...il.com>, Qiqi Wang <qiqi.wang@...iatek.com>, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org, linux-pm@...r.kernel.org,
netdev@...r.kernel.org, Project_Global_Chrome_Upstream_Group@...iatek.com,
sirius.wang@...iatek.com, vince-wl.liu@...iatek.com, jh.hsu@...iatek.com
Subject: Re: [PATCH v4 01/21] dt-bindings: clock: mediatek: Add MT8189 clock
definitions
On Mon, Dec 15, 2025 at 11:49:10AM +0800, irving.ch.lin wrote:
> From: Irving-CH Lin <irving-ch.lin@...iatek.com>
>
> Add device tree bindings for the clock of MediaTek MT8189 SoC.
You in different patchset already received that comment:
A nit, subject: drop second/last, redundant "bindings" or "definitions"
or whatever you keep adding here redundantly. The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
Can you finally read the docs?
>
> Signed-off-by: Irving-CH Lin <irving-ch.lin@...iatek.com>
> ---
> .../bindings/clock/mediatek,mt8189-clock.yaml | 90 +++
> .../clock/mediatek,mt8189-sys-clock.yaml | 58 ++
> .../dt-bindings/clock/mediatek,mt8189-clk.h | 580 ++++++++++++++++++
> 3 files changed, 728 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8189-clock.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8189-sys-clock.yaml
> create mode 100644 include/dt-bindings/clock/mediatek,mt8189-clk.h
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8189-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8189-clock.yaml
> new file mode 100644
> index 000000000000..d21e02df36a1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8189-clock.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mediatek,mt8189-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Functional Clock Controller for MT8189
> +
> +maintainers:
> + - Qiqi Wang <qiqi.wang@...iatek.com>
Why there is n ack for this? Is above person going to provide any
reviews? Why didn't this person review this binding, already at v4.
> +
> +description: |
> + The clock architecture in MediaTek like below
> + PLLs -->
> + dividers -->
> + muxes -->
> + clock gate
> +
> + The devices provide clock gate control in different IP blocks.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8189-camsys-main
> + - mediatek,mt8189-camsys-rawa
> + - mediatek,mt8189-camsys-rawb
> + - mediatek,mt8189-dbg-ao
> + - mediatek,mt8189-dem
> + - mediatek,mt8189-dispsys
> + - mediatek,mt8189-dvfsrc-top
> + - mediatek,mt8189-gce-d
> + - mediatek,mt8189-gce-m
> + - mediatek,mt8189-iic-wrap-e
> + - mediatek,mt8189-iic-wrap-en
> + - mediatek,mt8189-iic-wrap-s
> + - mediatek,mt8189-iic-wrap-ws
> + - mediatek,mt8189-imgsys1
> + - mediatek,mt8189-imgsys2
> + - mediatek,mt8189-infra-ao
> + - mediatek,mt8189-ipesys
> + - mediatek,mt8189-mdpsys
> + - mediatek,mt8189-mfgcfg
> + - mediatek,mt8189-mm-infra
> + - mediatek,mt8189-peri-ao
> + - mediatek,mt8189-scp-clk
> + - mediatek,mt8189-scp-i2c-clk
> + - mediatek,mt8189-ufscfg-ao
> + - mediatek,mt8189-ufscfg-pdn
> + - mediatek,mt8189-vdec-core
> + - mediatek,mt8189-venc
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt8189-peri-ao
> + - mediatek,mt8189-ufscfg-ao
> + - mediatek,mt8189-ufscfg-pdn
> +
> + then:
> + required:
> + - '#reset-cells'
else:
properties:
reset-cells: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@...21000 {
> + compatible = "mediatek,mt8189-iic-wrap-ws", "syscon";
> + reg = <0x11b21000 0x1000>;
> + #clock-cells = <1>;
> + };
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8189-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8189-sys-clock.yaml
> new file mode 100644
> index 000000000000..c94de207e289
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8189-sys-clock.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mediatek,mt8189-sys-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek System Clock Controller for MT8189
> +
> +maintainers:
> + - Qiqi Wang <qiqi.wang@...iatek.com>
Same problem. We are at v4 and maintainer did not bother to review it in
public. What sort of maintenance is this?
> +
> +description: |
> + The clock architecture in MediaTek like below
> + PLLs -->
> + dividers -->
> + muxes -->
> + clock gate
Pretty obvious, no? Is there a clock topology which is different?
> +
> + The apmixedsys provides most of PLLs which generated from SoC 26m.
> + The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
> + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
> + The mcusys provides mux control to select the clock source in AP MCU.
> + The device nodes also provide the system control capacity for configuration.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8189-apmixedsys
> + - mediatek,mt8189-topckgen
> + - mediatek,mt8189-vlpckgen
> + - mediatek,mt8189-vlp-ao
> + - mediatek,mt8189-vlpcfg-ao
> + - const: syscon
I do not understand why this is separate from the previous binding. It's
exactly the same, even description is the same.
Best regards,
Krzysztof
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