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Message-Id: <20251224-pci-msi-addr-mask-v1-4-05a6fcb4b4c0@iscas.ac.cn>
Date: Wed, 24 Dec 2025 11:10:52 +0800
From: Vivian Wang <wangruikang@...as.ac.cn>
To: Madhavan Srinivasan <maddy@...ux.ibm.com>,
Michael Ellerman <mpe@...erman.id.au>, Nicholas Piggin <npiggin@...il.com>,
"Christophe Leroy (CS GROUP)" <chleroy@...nel.org>,
Alex Deucher <alexander.deucher@....com>,
Christian König <christian.koenig@....com>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Brett Creeley <brett.creeley@....com>, Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Bjorn Helgaas <bhelgaas@...gle.com>, Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>
Cc: Han Gao <gaohan@...as.ac.cn>, linuxppc-dev@...ts.ozlabs.org,
linux-kernel@...r.kernel.org, amd-gfx@...ts.freedesktop.org,
dri-devel@...ts.freedesktop.org, netdev@...r.kernel.org,
linux-pci@...r.kernel.org, linux-sound@...r.kernel.org,
Vivian Wang <wangruikang@...as.ac.cn>
Subject: [PATCH 4/5] ALSA: hda/intel: Raise msi_addr_mask to dma_bits
The code was originally written using no_64bit_msi, which restricts the
device to 32-bit MSI addresses.
Since msi_addr_mask is introduced, use DMA_BIT_MASK(dma_bits) instead of
DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more
precisely and allowing these devices to work on platforms with MSI
doorbell address above 32-bit space, as long as it is within the
hardware's addressable space.
Signed-off-by: Vivian Wang <wangruikang@...as.ac.cn>
---
hda/intel maintainers: I don't know if this is the correct restriction.
Please help with checking. Thanks.
---
sound/hda/controllers/intel.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c
index c9542ebdf7e2..a44de2306a2b 100644
--- a/sound/hda/controllers/intel.c
+++ b/sound/hda/controllers/intel.c
@@ -1903,11 +1903,6 @@ static int azx_first_init(struct azx *chip)
chip->gts_present = true;
#endif
- if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
- dev_dbg(card->dev, "Disabling 64bit MSI\n");
- pci->msi_addr_mask = DMA_BIT_MASK(32);
- }
-
pci_set_master(pci);
gcap = azx_readw(chip, GCAP);
@@ -1958,6 +1953,11 @@ static int azx_first_init(struct azx *chip)
dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
dma_set_max_seg_size(&pci->dev, UINT_MAX);
+ if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
+ dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits);
+ pci->msi_addr_mask = DMA_BIT_MASK(dma_bits);
+ }
+
/* read number of streams from GCAP register instead of using
* hardcoded value
*/
--
2.51.2
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