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Message-ID: <20260107090441.954-1-javen_xu@realsil.com.cn>
Date: Wed, 7 Jan 2026 17:04:41 +0800
From: javen <javen_xu@...lsil.com.cn>
To: <hkallweit1@...il.com>
CC: <andrew+netdev@...n.ch>, <davem@...emloft.net>, <edumazet@...gle.com>,
<horms@...nel.org>, <javen_xu@...lsil.com.cn>, <kuba@...nel.org>,
<linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
<nic_swsd@...ltek.com>, <pabeni@...hat.com>
Subject: RE: [PATCH net-next 2/2] r8169: enable LTR support
> On 1/6/2026 9:30 AM, javen wrote:
> > From: Javen Xu <javen_xu@...lsil.com.cn>
> >
> > This patch will enable
> > RTL8168FP/RTL8168EP/RTL8168H/RTL8125/RTL8126/RTL8127 LTR support.
> >
> Few questions:
> - Is there a reason to ever disable LTR?
> - Is there any known LTR-related problem with the existing code?
> IOW: Should your patch be treated as a fix?
> - What is the chip default after a hw reset? Is LTR enabled or disabled?
> - Can at least some register numbers (and bits in these registers) be replaced with
> names according to the data sheet? I think of OCP reg 0xe032 and register 0xb6.
We generally do not recommend disabling LTR. LTR works in concert
with ASPM to reduce power consumption while maintaining performance.
There is no LTR-related bug in the existing code. The issue observed
on the customer's evaluation platform is that the link cannot enter
L1.1/L1.2 without LTR support. This patch enables LTR to allow the
device and platform to reach those low power states. Therefore, this
patch should be considered as a new feature.
After a hardware reset, LTR Enable defaults to 0 (disabled). Driver
must program the related registers to enable LTR.
We will replace some register numbers with names according to the
datasheet in the next patch.
> > Signed-off-by: Javen Xu <javen_xu@...lsil.com.cn>
> > ---
> > drivers/net/ethernet/realtek/r8169_main.c | 98
> > +++++++++++++++++++++++
> > 1 file changed, 98 insertions(+)
> >
> > diff --git a/drivers/net/ethernet/realtek/r8169_main.c
> > b/drivers/net/ethernet/realtek/r8169_main.c
> > index f9df6aadacce..97abf95502dc 100644
> > --- a/drivers/net/ethernet/realtek/r8169_main.c
> > +++ b/drivers/net/ethernet/realtek/r8169_main.c
> > @@ -2919,6 +2919,101 @@ static void rtl_disable_exit_l1(struct rtl8169_private *tp)
> > }
> > }
> >
> > +static void rtl_enable_ltr(struct rtl8169_private *tp) {
> > + switch (tp->mac_version) {
> > + case RTL_GIGA_MAC_VER_80:
> > + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003);
> > + r8168_mac_ocp_modify(tp, 0xe034, 0x0000, 0xc000);
> > + r8168_mac_ocp_modify(tp, 0xe0a2, 0x0000, BIT(0));
> > + r8168_mac_ocp_write(tp, 0xcdd2, 0x8c09);
> > + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdd4, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdda, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcddc, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcde8, 0x887a);
> > + r8168_mac_ocp_write(tp, 0xcdea, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdec, 0x8c09);
> > + r8168_mac_ocp_write(tp, 0xcdee, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdf0, 0x8a62);
> > + r8168_mac_ocp_write(tp, 0xcdf2, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdf4, 0x883e);
> > + r8168_mac_ocp_write(tp, 0xcdf6, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdf8, 0x8849);
> > + r8168_mac_ocp_write(tp, 0xcdfa, 0x9003);
> > + r8168_mac_ocp_modify(tp, 0xe032, 0x0000, BIT(14));
> > + break;
> > + case RTL_GIGA_MAC_VER_70:
> > + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003);
> > + r8168_mac_ocp_modify(tp, 0xe034, 0x0000, 0xc000);
> > + r8168_mac_ocp_modify(tp, 0xe0a2, 0x0000, BIT(0));
> > + r8168_mac_ocp_write(tp, 0xcdd2, 0x8c09);
> > + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdd4, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdda, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcddc, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcde8, 0x887a);
> > + r8168_mac_ocp_write(tp, 0xcdea, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdec, 0x8c09);
> > + r8168_mac_ocp_write(tp, 0xcdee, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdf0, 0x8a62);
> > + r8168_mac_ocp_write(tp, 0xcdf2, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdf4, 0x883e);
> > + r8168_mac_ocp_write(tp, 0xcdf6, 0x9003);
> > + r8168_mac_ocp_modify(tp, 0xe032, 0x0000, BIT(14));
> > + break;
> > + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
> > + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003);
> > + r8168_mac_ocp_modify(tp, 0xe034, 0x0000, 0xc000);
> > + r8168_mac_ocp_modify(tp, 0xe0a2, 0x0000, BIT(0));
> > + r8168_mac_ocp_write(tp, 0xcdd2, 0x889c);
> > + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c30);
> > + r8168_mac_ocp_write(tp, 0xcdda, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcddc, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcde8, 0x883e);
> > + r8168_mac_ocp_write(tp, 0xcdea, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdec, 0x889c);
> > + r8168_mac_ocp_write(tp, 0xcdee, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdf0, 0x8C09);
> > + r8168_mac_ocp_write(tp, 0xcdf2, 0x9003);
> > + r8168_mac_ocp_modify(tp, 0xe032, 0x0000, BIT(14));
> > + break;
> > + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_52:
> > + r8168_mac_ocp_modify(tp, 0xe034, 0x0000, 0xc000);
> > + r8168_mac_ocp_modify(tp, 0xe0a2, 0x0000, BIT(0));
> > + r8168_mac_ocp_write(tp, 0xe02c, 0x1880);
> > + r8168_mac_ocp_write(tp, 0xe02e, 0x4880);
> > + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdda, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcddc, 0x9003);
> > + r8168_mac_ocp_write(tp, 0xcdd2, 0x883c);
> > + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12);
> > + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003);
> > + RTL_W8(tp, 0xb6, RTL_R8(tp, 0xb6) | BIT(0));
> > + break;
> > + default:
> > + return;
> > + }
> > + /* chip can trigger LTR */
> > + r8168_mac_ocp_modify(tp, 0xe032, 0x0003, BIT(0)); }
> > +
> > +static void rtl_disable_ltr(struct rtl8169_private *tp) {
> > + switch (tp->mac_version) {
> > + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_80:
> > + r8168_mac_ocp_modify(tp, 0xe032, 0x0003, 0);
> > + break;
> > + default:
> > + break;
> > + }
> > +}
> > +
> > static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp,
> > bool enable) {
> > u8 val8;
> > @@ -2947,6 +3042,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
> > break;
> > }
> >
> > + rtl_enable_ltr(tp);
> > switch (tp->mac_version) {
> > case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
> > case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
> > @@ -2968,6 +3064,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
> > break;
> > }
> >
> > + rtl_disable_ltr(tp);
> > switch (tp->mac_version) {
> > case RTL_GIGA_MAC_VER_70:
> > case RTL_GIGA_MAC_VER_80:
> > @@ -4811,6 +4908,7 @@ static void rtl8169_down(struct rtl8169_private
> > *tp)
> >
> > rtl8169_cleanup(tp);
> > rtl_disable_exit_l1(tp);
> > + rtl_disable_ltr(tp);
> > rtl_prepare_power_down(tp);
> >
> > if (tp->dash_type != RTL_DASH_NONE && !tp->saved_wolopts)
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