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Message-ID: <b19d87c3-e783-44d1-ae7c-5911ba42d487@samsung.com>
Date: Thu, 8 Jan 2026 14:59:05 +0100
From: Marek Szyprowski <m.szyprowski@...sung.com>
To: "Michael S. Tsirkin" <mst@...hat.com>, linux-kernel@...r.kernel.org
Cc: Cong Wang <xiyou.wangcong@...il.com>, Jonathan Corbet <corbet@....net>,
Olivia Mackall <olivia@...enic.com>, Herbert Xu
<herbert@...dor.apana.org.au>, Jason Wang <jasowang@...hat.com>, Paolo
Bonzini <pbonzini@...hat.com>, Stefan Hajnoczi <stefanha@...hat.com>,
Eugenio Pérez <eperezma@...hat.com>, "James E.J. Bottomley"
<James.Bottomley@...senpartnership.com>, "Martin K. Petersen"
<martin.petersen@...cle.com>, Gerd Hoffmann <kraxel@...hat.com>, Xuan Zhuo
<xuanzhuo@...ux.alibaba.com>, Robin Murphy <robin.murphy@....com>, Stefano
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Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo
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Subject: Re: [PATCH v2 04/15] docs: dma-api: document
DMA_ATTR_CPU_CACHE_CLEAN
On 05.01.2026 09:23, Michael S. Tsirkin wrote:
> Document DMA_ATTR_CPU_CACHE_CLEAN as implemented in the
> previous patch.
>
> Signed-off-by: Michael S. Tsirkin <mst@...hat.com>
Acked-by: Marek Szyprowski <m.szyprowski@...sung.com>
> ---
> Documentation/core-api/dma-attributes.rst | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst
> index 0bdc2be65e57..1d7bfad73b1c 100644
> --- a/Documentation/core-api/dma-attributes.rst
> +++ b/Documentation/core-api/dma-attributes.rst
> @@ -148,3 +148,12 @@ DMA_ATTR_MMIO is appropriate.
> For architectures that require cache flushing for DMA coherence
> DMA_ATTR_MMIO will not perform any cache flushing. The address
> provided must never be mapped cacheable into the CPU.
> +
> +DMA_ATTR_CPU_CACHE_CLEAN
> +------------------------
> +
> +This attribute indicates the CPU will not dirty any cacheline overlapping this
> +DMA_FROM_DEVICE/DMA_BIDIRECTIONAL buffer while it is mapped. This allows
> +multiple small buffers to safely share a cacheline without risk of data
> +corruption, suppressing DMA debug warnings about overlapping mappings.
> +All mappings sharing a cacheline should have this attribute.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
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