netdev - Re: [PATCH net-next v3 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add phy

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Message-ID: <176849859188.929140.12375075368934726420.robh@kernel.org>
Date: Thu, 15 Jan 2026 11:36:32 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Jakub Kicinski <kuba@...nel.org>, netdev@...r.kernel.org,
	Magnus Damm <magnus.damm@...il.com>,
	linux-renesas-soc@...r.kernel.org,
	Heiner Kallweit <hkallweit1@...il.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Biju Das <biju.das.jz@...renesas.com>,
	Eric Dumazet <edumazet@...gle.com>,
	"David S. Miller" <davem@...emloft.net>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Clément Léger <clement.leger@...tlin.com>,
	linux-kernel@...r.kernel.org,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	Andrew Lunn <andrew+netdev@...n.ch>, devicetree@...r.kernel.org,
	Paolo Abeni <pabeni@...hat.com>,
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
	Conor Dooley <conor+dt@...nel.org>,
	Russell King <linux@...linux.org.uk>
Subject: Re: [PATCH net-next v3 1/2] dt-bindings: net: pcs:
 renesas,rzn1-miic: Add phy_link property


On Mon, 12 Jan 2026 17:35:54 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> 
> Add the renesas,miic-phy-link-active-low property to allow configuring
> the active level of phy_link status signals provided by the MIIC block.
> 
> EtherPHY link-up and link-down status is required as a hardware IP
> feature independent of whether GMAC or ETHSW is used. With GMAC, link
> state is retrieved via MDC/MDIO and handled in software. In contrast,
> ETHSW exposes dedicated PHY_LINK pins that provide this information
> directly in hardware.
> 
> These PHY_LINK signals are required not only for host-controlled traffic
> but also for switch-only forwarding paths where frames are exchanged
> between external nodes without CPU involvement. This is particularly
> important for redundancy protocols such as DLR (Device Level Ring),
> which depend on fast detection of link-down events caused by cable or
> port failures. Handling such events purely in software introduces
> latency, which is why ETHSW provides dedicated hardware PHY_LINK pins.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v2->v3:
> - Updated commit message
> - Renamed DT property from renesas,miic-phylink-active-low to
>   renesas,miic-phy-link-active-low.
> 
> v1->v2:
> - Updated commit message to elaborate the necessity of PHY link signals.
> ---
>  .../devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml     | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@...nel.org>