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Message-ID: <20260121151506.813783-2-dam.dejean@gmail.com>
Date: Wed, 21 Jan 2026 16:15:04 +0100
From: Damien Dejean <dam.dejean@...il.com>
To: andrew@...n.ch,
krzk+dt@...nel.org
Cc: netdev@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
edumazet@...gle.com,
davem@...emloft.net,
kuba@...nel.org,
pabeni@...hat.com,
hkallweit1@...il.com,
Damien Dejean <dam.dejean@...il.com>
Subject: [PATCH v2 2/4] net: phy: realtek: add RTL8224 pair order support
The RTL8224 has a register to configure a pair swap (from ABCD order to
DCBA) providing PCB designers more flexbility when wiring the chip. The
swap parameter has to be set correctly for each of the 4 ports before
the chip can detect a link.
After a reset, this register is (unfortunately) left in a random state,
thus it has to be initialized. On most of the devices the bootloader
does it once for all and we can rely on the value set, on some other it
is not and the kernel has to do it.
The MDI pair swap can be set in the device tree using the property
realtek,mdi-cfg-order. The property is set to 0 to keep the default
order (ABCD), or 1 to reverse the pairs (DCBA).
Signed-off-by: Damien Dejean <dam.dejean@...il.com>
---
drivers/net/phy/realtek/Kconfig | 1 +
drivers/net/phy/realtek/realtek_main.c | 50 ++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/drivers/net/phy/realtek/Kconfig b/drivers/net/phy/realtek/Kconfig
index b05c2a1e9024..a741b34d193e 100644
--- a/drivers/net/phy/realtek/Kconfig
+++ b/drivers/net/phy/realtek/Kconfig
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config REALTEK_PHY
tristate "Realtek PHYs"
+ select PHY_PACKAGE
help
Currently supports RTL821x/RTL822x and fast ethernet PHYs
diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
index 6ff0385201a5..85b0eea936e4 100644
--- a/drivers/net/phy/realtek/realtek_main.c
+++ b/drivers/net/phy/realtek/realtek_main.c
@@ -18,6 +18,7 @@
#include <linux/clk.h>
#include <linux/string_choices.h>
+#include "../phylib.h"
#include "realtek.h"
#define RTL8201F_IER 0x13
@@ -162,6 +163,8 @@
#define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4)
+#define RTL8224_VND1_MDI_PAIR_SWAP 0xa90
+
#define RTL8366RB_POWER_SAVE 0x15
#define RTL8366RB_POWER_SAVE_ON BIT(12)
@@ -1683,6 +1686,51 @@ static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finish
return rtl8224_cable_test_report(phydev, finished);
}
+static int rtl8224_mdi_config_order(struct phy_device *phydev)
+{
+ struct device_node *np = phydev->mdio.dev.of_node;
+ u8 port_offset = phydev->mdio.addr & 3;
+ u32 mdi_conf, val;
+ int ret;
+
+ ret = of_property_read_u32(np, "realtek,mdi-cfg-order", &mdi_conf);
+
+ /* Do nothing in case the property is not present */
+ if (ret == -EINVAL)
+ return 0;
+
+ if (ret)
+ return ret;
+
+ if (mdi_conf & ~1)
+ return -EINVAL;
+
+ val = __phy_package_read_mmd(phydev, 0, MDIO_MMD_VEND1,
+ RTL8224_VND1_MDI_PAIR_SWAP);
+ if (val < 0)
+ return val;
+
+ if (mdi_conf)
+ val |= (1 << port_offset);
+ else
+ val &= ~(1 << port_offset);
+
+ return __phy_package_write_mmd(phydev, 0, MDIO_MMD_VEND1,
+ RTL8224_VND1_MDI_PAIR_SWAP, val);
+}
+
+static int rtl8224_config_init(struct phy_device *phydev)
+{
+ return rtl8224_mdi_config_order(phydev);
+}
+
+static int rtl8224_probe(struct phy_device *phydev)
+{
+ /* Chip exposes 4 ports, join all of them in the same package */
+ return devm_phy_package_join(&phydev->mdio.dev, phydev,
+ phydev->mdio.addr & ~3, 0);
+}
+
static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
{
int val;
@@ -2212,6 +2260,8 @@ static struct phy_driver realtek_drvs[] = {
PHY_ID_MATCH_EXACT(0x001ccad0),
.name = "RTL8224 2.5Gbps PHY",
.flags = PHY_POLL_CABLE_TEST,
+ .probe = rtl8224_probe,
+ .config_init = rtl8224_config_init,
.get_features = rtl822x_c45_get_features,
.config_aneg = rtl822x_c45_config_aneg,
.read_status = rtl822x_c45_read_status,
--
2.47.3
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