| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <15accbfe16853a468890944dbf75de46ef560f83.camel@microchip.com>
Date: Fri, 23 Jan 2026 16:12:18 +0100
From: Jens Emil Schulz Ostergaard <jensemil.schulzostergaard@...rochip.com>
To: Oleksij Rempel <o.rempel@...gutronix.de>
CC: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>, "David S. Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski
<kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Horatiu Vultur
<horatiu.vultur@...rochip.com>, Steen Hegelund
<Steen.Hegelund@...rochip.com>, Daniel Machon <daniel.machon@...rochip.com>,
<netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<kernel@...gutronix.de>, <rsc@...gutronix.de>
Subject: Re: [PATCH net-next] net: phy: micrel: Add support for lan9645x
internal phy
Hi Oleksij,
On Fri, 2026-01-23 at 10:55 +0100, Oleksij Rempel wrote:
>
> Hi Jens,
>
> On Fri, Jan 23, 2026 at 08:50:55AM +0100, Jens Emil Schulz Østergaard wrote:
> > LAN9645X is a family of switch chips with 5 internal copper phys. The
> > internal PHY is based on parts of LAN8832. This is a low-power, single
> > port triple-speed (10BASE-T/100BASE-TX/1000BASE-T) ethernet physical
> > layer transceiver (PHY) that supports transmission and reception of data
> > on standard CAT-5, as well as CAT-5e and CAT-6 Unshielded Twisted
> > Pair (UTP) cables.
> >
> > Add support for the internal PHY of the lan9645x chip family.
>
> Looks like interesting switch for our use cases :)
>
> > Reviewed-by: Steen Hegelund <Steen.Hegelund@...rochip.com>
> > Reviewed-by: Daniel Machon <daniel.machon@...rochip.com>
> > Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@...rochip.com>
> > ---
> > drivers/net/phy/micrel.c | 142 +++++++++++++++++++++++++++++++++++++++++++++
> > include/linux/micrel_phy.h | 1 +
> > 2 files changed, 143 insertions(+)
> >
> > diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
> > index 225d4adf28be..7f47f7987067 100644
> > --- a/drivers/net/phy/micrel.c
> > +++ b/drivers/net/phy/micrel.c
> > @@ -6502,6 +6502,132 @@ static void lan8842_get_phy_stats(struct phy_device *phydev,
> > stats->tx_errors = priv->phy_stats.tx_errors;
> > }
> >
> > +#define LAN9645X_DAC_ICAS_AMP_POWER_DOWN 0x47
> > +#define LAN9645X_BTRX_QBIAS_POWER_DOWN 0x46
> > +#define LAN9645X_TX_LOW_I_CH_CD_POWER_MGMT 0x45
> > +#define LAN9645X_TX_LOW_I_CH_B_POWER_MGMT 0x44
> > +#define LAN9645X_TX_LOW_I_CH_A_POWER_MGMT 0x43
>
> > +static const struct lanphy_reg_data force_dac_tx_errata[] = {
> > + /* Force channel A/B/C/D TX on */
> > + { LAN8814_PAGE_POWER_REGS,
> > + LAN9645X_DAC_ICAS_AMP_POWER_DOWN,
> > + 0 },
> > + /* Force channel A/B/C/D QBias on */
> > + { LAN8814_PAGE_POWER_REGS,
> > + LAN9645X_BTRX_QBIAS_POWER_DOWN,
> > + 0xaa },
> > + /* tx low I on channel C/D overwrite */
> > + { LAN8814_PAGE_POWER_REGS,
> > + LAN9645X_TX_LOW_I_CH_CD_POWER_MGMT,
> > + 0xbfff },
> > + /* channel B low I overwrite */
> > + { LAN8814_PAGE_POWER_REGS,
> > + LAN9645X_TX_LOW_I_CH_B_POWER_MGMT,
> > + 0xabbf },
> > + /* channel A low I overwrite */
> > + { LAN8814_PAGE_POWER_REGS,
> > + LAN9645X_TX_LOW_I_CH_A_POWER_MGMT,
> > + 0xbd3f },
> > +};
>
> It looks like this erratum not publicly documented. At least not here:
> https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/Errata/LAN9645xS-
> LAN9645xF-Errata-DS80001187.pdf
>
> re there more information about it? Can it be described in the comment?
>
You are right, I think they ought to be documented in the official erratas
list with a more thorough description. I will get a hold of the right
people and ask them to add it.
> > +
> > +static int lan9645x_config_init(struct phy_device *phydev)
> > +{
> > + int ret;
> > +
> > + /* Apply erratas. */
> > + ret = lan8842_erratas(phydev);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return lanphy_write_reg_data(phydev, force_dac_tx_errata,
> > + ARRAY_SIZE(force_dac_tx_errata));
> > +}
> > +
> > +static int lan9645x_suspend(struct phy_device *phydev)
> > +{
> > + int aneg_en_state, ret;
> > +
> > + /* Software workaround from design to handle SPD. SPD will stop AFE
> > + * clock from AFE port, which makes the system MAC fifo unable to flush.
> > + * The workaround is to restart ANEG and wait for flush, before issuing
> > + * software power down.
> > + */
> > + aneg_en_state = phy_read(phydev, MII_BMCR) & BMCR_ANENABLE;
> > +
> > + ret = phy_restart_aneg(phydev);
> > + if (ret)
> > + return ret;
> > +
> > + /* Allow time for system FIFO flush data */
> > + usleep_range(8 * USEC_PER_MSEC, 12 * USEC_PER_MSEC);
>
> MAC and PHY power management are not always fully coupled (implementation
> specific), are there other ways to sync them with each other, except of
> unconditional sleep in the PHY driver. I expect that someone making
> changes on the MAC driver may miss this nuance.
>
The MAC side will be handled in a yet-to-be-sent DSA driver, which is also
authored by my team.
During development I was seeing issues where SPD sometimes causing
interference on neighbouring PHYs. The PHY team came up with the tx dac
errata and the aneg restart workaround as a solution.
To my knowledge there was no alternative workaround, but I have reached out
to the PHY team to make sure. If there is a better way to fix these issues,
I will add it in the next version.
> Best Regards,
> Oleksij
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Thank you for the comments,
Emil
Powered by blists - more mailing lists