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Message-ID: <20260125200259.2903271-1-dam.dejean@gmail.com>
Date: Sun, 25 Jan 2026 21:02:56 +0100
From: Damien Dejean <dam.dejean@...il.com>
To: andrew@...n.ch,
krzk+dt@...nel.org,
robh@...nel.org
Cc: netdev@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
edumazet@...gle.com,
davem@...emloft.net,
kuba@...nel.org,
pabeni@...hat.com,
hkallweit1@...il.com,
Damien Dejean <dam.dejean@...il.com>
Subject: [PATCH v3 1/4] dt-bindings: net: ethernet-phy: add property enet-phy-lane-order
Add property enet-phy-lane-order to the device tree bindings to define
the lane order of the PHY. To simplify PCB design some manufacturers
allow to wire the pairs in a reverse order, and change the order in
software.
The property can be set to 0 to force the normal lane order (ABCD), or 1
to force the reverse lane order (DCBA).
Signed-off-by: Damien Dejean <dam.dejean@...il.com>
---
Documentation/devicetree/bindings/net/ethernet-phy.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
index bb4c49fc5fd8..b8cd5d2b9f76 100644
--- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
@@ -126,6 +126,12 @@ properties:
e.g. wrong bootstrap configuration caused by issues in PCB
layout design.
+ enet-phy-lane-order:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description:
+ For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA).
+
eee-broken-100tx:
$ref: /schemas/types.yaml#/definitions/flag
description:
base-commit: 983d014aafb14ee5e4915465bf8948e8f3a723b5
--
2.47.3
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