netdev - Re: [PATCH 2/4] phy: s32g: Add serdes subsystem phy

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <69592713b7bd419e23df458734ca78070a83e8ac.camel@pengutronix.de>
Date: Mon, 26 Jan 2026 14:11:15 +0100
From: Philipp Zabel <p.zabel@...gutronix.de>
To: Vincent Guittot <vincent.guittot@...aro.org>, vkoul@...nel.org, 
	neil.armstrong@...aro.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
	ciprianmarian.costea@....nxp.com, s32@....com, linux@...linux.org.uk, 
	ghennadi.procopciuc@....com, bogdan-gabriel.roman@....com,
 Ionut.Vicovan@....com, 	alexandru-catalin.ionita@....com,
 linux-phy@...ts.infradead.org, 	devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, 	linux-arm-kernel@...ts.infradead.org,
 netdev@...r.kernel.org
Cc: Frank.li@....com
Subject: Re: [PATCH 2/4] phy: s32g: Add serdes subsystem phy

On Mo, 2026-01-26 at 10:21 +0100, Vincent Guittot wrote:
> s32g SoC family includes 2 serdes subsystems which are made of one PCIe
> controller, 2 XPCS and one Phy. The Phy got 2 lanes that can be configure
> to output PCIe lanes and/or SGMII.
> 
> Implement PCIe phy support
> 
> Co-developed-by: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
> Co-developed-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@....com>
> Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@....com>
> Co-developed-by: Ghennadi Procopciuc <ghennadi.procopciuc@....com>
> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@....com>
> Co-developed-by: Ionut Vicovan <Ionut.Vicovan@....com>
> Signed-off-by: Ionut Vicovan <Ionut.Vicovan@....com>
> Co-developed-by: Bogdan Roman <bogdan-gabriel.roman@....com>
> Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@....com>
> Signed-off-by: Vincent Guittot <vincent.guittot@...aro.org>
> ---
>  drivers/phy/freescale/Kconfig               |   9 +
>  drivers/phy/freescale/Makefile              |   1 +
>  drivers/phy/freescale/phy-nxp-s32g-serdes.c | 569 ++++++++++++++++++++
>  3 files changed, 579 insertions(+)
>  create mode 100644 drivers/phy/freescale/phy-nxp-s32g-serdes.c
> 
[...]
> diff --git a/drivers/phy/freescale/phy-nxp-s32g-serdes.c b/drivers/phy/freescale/phy-nxp-s32g-serdes.c
> new file mode 100644
> index 000000000000..8336c868c8dc
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-nxp-s32g-serdes.c
> @@ -0,0 +1,569 @@
[...]
> +static int s32g_serdes_get_ctrl_resources(struct platform_device *pdev, struct s32g_serdes *serdes)
> +{
[...]
> +	ctrl->rst = devm_reset_control_get(dev, "serdes");

Please use devm_reset_control_get_exclusive() directly.

[...]
> +static int s32g_serdes_get_pcie_resources(struct platform_device *pdev, struct s32g_serdes *serdes)
> +{
[...]
> +	pcie->rst = devm_reset_control_get(dev, "pcie");

Same here.

regards
Philipp