netdev - Re: [PATCH net-next v2] declance: Remove IRQF

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Message-ID: <20260127165430.7ui_LGkg@linutronix.de>
Date: Tue, 27 Jan 2026 17:54:30 +0100
From: Sebastian Andrzej Siewior <bigeasy@...utronix.de>
To: "Maciej W. Rozycki" <macro@...am.me.uk>
Cc: netdev@...r.kernel.org, linux-mips@...r.kernel.org,
	Jakub Kicinski <kuba@...nel.org>,
	Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>, Paolo Abeni <pabeni@...hat.com>
Subject: Re: [PATCH net-next v2] declance: Remove IRQF_ONESHOT

On 2026-01-27 15:46:10 [+0000], Maciej W. Rozycki wrote:
> On Tue, 27 Jan 2026, Sebastian Andrzej Siewior wrote:
> 
> > The IRQF_ONESHOT flag was added in commit 0fabe1021f8bc ("MIPS:
> > DECstation I/O ASIC DMA interrupt classes"). It moved
> > clear_ioasic_dma_irq() from the driver into the irq-chip.
> > For EOI interrupts the clear_ioasic_dma_irq() callback is now invoked as
> > ->irq_eoi() which is invoked after the IRQ was handled while the
> > interrupt is masked due to IRQF_ONESHOT. Without IRQF_ONESHOT it would
> > be invoked while interrupt is unmasked (but interrupts are disabled).
> 
>  Umm, are they?  It's been a while, but have I missed anything?  As I 
> recall ->irq_mask() is called exactly so that interrupts can be re-enabled 
> at the CPU level right way so as not to block other sources which may have 
> a low latency requirement while a hardirq handler is running.

A hardirq is always serviced with disabled interrupts from CPU point of
view. There were exceptions in the IDE department as far as I remember
where it was possible to enable interrupts from CPUs point of view while
the interrupt was serviced. That was 2.2/2.4 time frame and edge
interrupts made it possible.

It is not required to mask the interrupt while the handler is invoked
unless it is required to properly ACK the interrupt from device's and
IRQ-chip point of view.
The sole purpose of IRQF_ONESHOT was to disable the interrupt source
while the threaded interrupt is running. This driver has none.

> > If it is *required* to invoke EOI-ack while the interrupt is masked (and
> > not a misunderstanding) due to irq-chip cascading/ hierarchical reasons
> > then using handle_fasteoi_mask_irq() as flow-handler would be the right
> > way to do so.
> 
>  Since this is a level-triggered interrupt unmasking it before the EOI 
> will make it retrigger right away and loop forever.  And as the 
> description of commit 0fabe1021f8b ("MIPS: DECstation I/O ASIC DMA 
> interrupt classes") says the interrupt must not be acked before EOI, as 
> the problematic transfer would restart while the IRQ handler is still 
> running:

If it is a level interrupt and MASK/ACK in the irq-chip then the device
will issue the interrupt again if the source of the interrupt (i.e. the
error) has not been solved. Since the handler does only a printk() it
should trigger again.

> 16 R/W0C LANCE DMA memory read error
>          This bit is set to 1 and DMA disabled, when the LANCE DMA
>          encounters a memory read error. The LANCE then times out and
>          interrupts the processor, which handles the problem. The LPR can
>          read the address of the error. The bit may be cleared by writing a 0;
>          writing a 1 has no effect.
> 
> so a combined ACK-EOI is the only correct way to handle it.

Make sense. So first the driver needs to set this bit and then IRQ-chip
would need to see the EOI after the handler run. You would still need to
cancel/ tear down the transfer before that.

Again, with the interrupt handler setup as-is lance_dma_merr_int() will
run with disabled interrupts.

>  Yes, the handler is sort of a placeholder, but the structure of handling 
> ought to be correct regardless.
> 
>  One issue here is this is a recovery handler for an error scenario that 
> is not supposed to happen with a correctly operating system.  I've never 
> seen it actually fire, which is also why there's no actual recovery action 
> implemented.  Perhaps such an error could be induced for verification 
> purposes, I don't know.  All in all this code may have to rely solely on 
> hw specs.
> 
>  I need more data to conclude whether this is the right change to make I'm 
> afraid.  Thank you for looking into it though.

Fair enough. Would it work for you if we scratch this from net-next and
you route this or something else via the mips tree?

>   Maciej

Sebastian