netdev - Re: [PATCH net-next v9 0/4] net: dsa: initial support for MaxLinear MxL862xx switches

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Message-ID: <20260127225643.qe4lpeyjmtl6flc4@skbuf>
Date: Wed, 28 Jan 2026 00:56:43 +0200
From: Vladimir Oltean <olteanv@...il.com>
To: Daniel Golle <daniel@...rotopia.org>
Cc: Andrew Lunn <andrew@...n.ch>, "David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	Simon Horman <horms@...nel.org>, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	Frank Wunderlich <frankwu@....de>, Chad Monroe <chad@...roe.io>,
	Cezary Wilmanski <cezary.wilmanski@...ran.com>,
	Avinash Jayaraman <ajayaraman@...linear.com>,
	Bing tao Xu <bxu@...linear.com>, Liang Xu <lxu@...linear.com>,
	Juraj Povazanec <jpovazanec@...linear.com>,
	"Fanni (Fang-Yi) Chan" <fchan@...linear.com>,
	"Benny (Ying-Tsan) Weng" <yweng@...linear.com>,
	"Livia M. Rosu" <lrosu@...linear.com>,
	John Crispin <john@...ozen.org>
Subject: Re: [PATCH net-next v9 0/4] net: dsa: initial support for MaxLinear
 MxL862xx switches

On Tue, Jan 27, 2026 at 09:37:40PM +0000, Daniel Golle wrote:
> This series adds very basic DSA support for the MaxLinear MxL86252
> (5 PHY ports) and MxL86282 (8 PHY ports) switches.
> 
> MxL862xx integrates a firmware running on an embedded processor (running
> Zephyr RTOS). Host interaction uses a simple netlink-like API transported
> over MDIO/MMD.
> 
> This series includes only what's needed to pass traffic between user
> ports and the CPU port: relayed MDIO to internal PHYs, basic port
> enable/disable, and CPU-port special tagging.
> Follow up series will bring bridge, VLAN, ... offloading,

I'm surprised the Kconfig help text says:

	  These switches have two 10GE SerDes interfaces, one typically
	  used as CPU port.

yet only PHY_INTERFACE_MODE_INTERNAL is set in phylink supported_interfaces.
You're also not making any mention of future SerDes support. What's up
with that, how do the SerDes ports currently work and how are they
described? (as internal?!)

> and support for using a 802.1Q-based special tag instead of the
> proprietary 8-byte tag.

Why is that?

Another (related) question. You have this comment in tag_mxl862xx.c:

	/* switch firmware expects ports to be counted starting from 1 */

from which I don't completely understand how is the firmware involved
(does it process the tags?). Would the expectation also apply to the
802.1Q based tagger?

What's the real story behind port index 0? Does it really not exist, or
is it some attempt to hide an internal port that's not supposed to be used?

If the latter, I guess something like the snippet below (seen in
arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts) would simplify
the driver by a bit:

	ethernet-switch@0 {
		...
		ethernet-ports {
			...
			/* Microcontroller port */
			port@0 {
				reg = <0>;
				status = "disabled";
			};