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Message-ID: <e5751b33-4650-4b9f-8b9d-7f9297b1e67d@molgen.mpg.de>
Date: Fri, 30 Jan 2026 00:45:33 +0100
From: Paul Menzel <pmenzel@...gen.mpg.de>
To: Jacob Keller <jacob.e.keller@...el.com>
Cc: intel-wired-lan@...ts.osuosl.org, netdev@...r.kernel.org,
przemyslaw.korba@...el.com,
Aleksandr Loktionov <aleksandr.loktionov@...el.com>
Subject: Re: [Intel-wired-lan] [PATCH iwl-next] i40e: only timestamp PTP event
packets
Dear Jacob,
Thank you for the patch.
Am 29.01.26 um 22:52 schrieb Jacob Keller:
> The i40e_ptp_set_timestamp_mode() function is responsible for configuring
> hardware timestamping. When programming receive timestamping, the logic
> must determine how to configure the PRTTSYN_CTL1 register for receive
> timestamping.
>
> The i40e hardware does not support timestamping all frames. Instead,
> timestamps are captured into one of the four PRTTSYN_RXTIME registers.
>
> Currently, the driver configures hardware to timestamp all V2 packets on
> ports 319 and 320, including all message types. This timestamps
> significantly more packets than is actually requested by the
> HWTSTAMP_FILTER_PTP_V2_EVENT filter type.
>
> The documentation for HWTSTAMP_FILTER_PTP_V2_EVENT indicates that it should
> timestamp PTP v2 messages on any layer, including any kind of event
> packets.
>
> Timestamping other packets is acceptable, but not required by the filter.
> Doing so wastes valuable slots in the Rx timestamp registers. For most
> applications this doesn't cause a problem. However, for extremely high
> rates of messages, it becomes possible that one of the critical event
> packets is not timestamped.
>
> The PTP protocol only requires timestamps for event messages on port 319,
> but hardware is timestamping on both 319 and 320, and timestamping message
> types which do not need a timestamp value.
>
> The i40e hardware actually has a more strict filtering option. First, only
> timestamp layer 4 messages on port 319 instead of both 319 and 320. Second,
> note that hardware has a specific mode to timestamp only event packets
> (those with message type < 8).
>
> Update the configuration to use this mode, so that timestamps are captured
> for only event messages. This replaces the use of the 'wildcard' option of
> the V2MESSTYPE field which caused timestamping of all message types
> regardless of whether it was an event message.
>
> This avoids wasting the valuable Rx timestamp register slots on non-event
> frames, and may reduce faults when operating under high event rates.
Do you have a test case to reproduce this?
Can the other mode be enabled somehow for people needing port 320 and
timestamps on every message?
> Signed-off-by: Jacob Keller <jacob.e.keller@...el.com>
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@...el.com>
> ---
> drivers/net/ethernet/intel/i40e/i40e_register.h | 10 ++++++++++
> drivers/net/ethernet/intel/i40e/i40e_ptp.c | 9 +++------
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h
> index c4051dbcc297..2560c47910d4 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_register.h
> +++ b/drivers/net/ethernet/intel/i40e/i40e_register.h
> @@ -797,8 +797,18 @@
> #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16
> #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT)
> #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24
> +#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
> +/* Timestamp UDP v1 packets */
> +#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 \
> + FIELD_PREP(I40E_PRTTSYN_CTL1_TSYNTYPE_MASK, 1)
> +/* Timestamp L2 and UDP v2 packets with message type < 8 */
> +#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2_EVENT \
> + FIELD_PREP(I40E_PRTTSYN_CTL1_TSYNTYPE_MASK, 3)
> #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26
> #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT)
> +/* Timestamp UDP packets on port 319 */
> +#define I40E_PRTTSYN_CTL1_UDP_ENA_319 \
> + FIELD_PREP(I40E_PRTTSYN_CTL1_UDP_ENA_MASK, 1)
> #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31
> #define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT)
> #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_ptp.c b/drivers/net/ethernet/intel/i40e/i40e_ptp.c
> index 89abe2f22216..d70adf2e5a1c 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_ptp.c
> +++ b/drivers/net/ethernet/intel/i40e/i40e_ptp.c
> @@ -24,9 +24,6 @@
> #define I40E_PTP_1GB_INCVAL_MULT 20
> #define I40E_ISGN 0x80000000
>
> -#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
> -#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \
> - I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
> #define I40E_SUBDEV_ID_25G_PTP_PIN 0xB
>
> enum i40e_ptp_pin {
> @@ -1278,7 +1275,7 @@ static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
> pf->ptp_rx = true;
> tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
> I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
> - I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
> + I40E_PRTTSYN_CTL1_UDP_ENA_319;
> config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
> break;
> case HWTSTAMP_FILTER_PTP_V2_EVENT:
> @@ -1295,9 +1292,9 @@ static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
> case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
> pf->ptp_rx = true;
> tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
> - I40E_PRTTSYN_CTL1_TSYNTYPE_V2;
> + I40E_PRTTSYN_CTL1_TSYNTYPE_V2_EVENT;
> if (test_bit(I40E_HW_CAP_PTP_L4, pf->hw.caps)) {
> - tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
> + tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_319;
> config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
> } else {
> config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
Kind regards,
Paul
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