netdev - Re: [PATCH net-next v3] net: ethernet: mtk_eth_soc: avoid writing to ESW registers on MT7628

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Message-ID: <aXrvPyNSkNSFTjR7@plutus>
Date: Thu, 29 Jan 2026 08:22:40 +0200
From: Joris Vaišvila <joey@...yisr.com>
To: Jakub Kicinski <kuba@...nel.org>
Cc: netdev@...r.kernel.org, nbd@....name, sean.wang@...iatek.com, 
	lorenzo@...nel.org, andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com, 
	pabeni@...hat.com
Subject: Re: [PATCH net-next v3] net: ethernet: mtk_eth_soc: avoid writing to
 ESW registers on MT7628

> > +static void rt5350_mac_config(struct phylink_config *config, unsigned int mode,
> > +				const struct phylink_link_state *state)
> > +{
> > +}
> > +
> > +static void rt5350_mac_link_down(struct phylink_config *config, unsigned int mode,
> > +				phy_interface_t interface)
> > +{
> > +}
> > +
> > +static void rt5350_mac_link_up(struct phylink_config *config,
> > +			    struct phy_device *phy,
> > +			    unsigned int mode, phy_interface_t interface,
> > +			    int speed, int duplex, bool tx_pause, bool rx_pause)
> > +{
> > +}
> 
> Is there any other driver that implements fixed link with phylink this
> way? I know regrettably little about phylink. I'd think that mac up/down
> usually would still do _something_.
> 

`net/dsa/port.c` stubs are the only other place with no-op phylink mac
ops.

On MT7628, the existing `mtk_gdm_mac_link_up()` does not actually
commit any configuration to the MAC hardware. The only potentially
observable change is `mac->speed = speed`, however leaving that as
`UNKNOWN_SPEED` appears more accurate for this SoC, though I will
recheck for side-effects of that.

`mtk_mac_link_down()` also does not touch any valid MAC registers. Both
of these functions are already effectively no-ops in terms of MAC
configuration on this SoC. They only clobber unrelated ESW registers.

While the ESW block seems to provide a way to control the CPU port speed
and link state, this is a separate IP and I don't think it's appropriate
to have the MAC driver program it.

While I'm not very familiar with phylink either, this is no different
from how the original driver handles link up/down on this SoC.