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Message-Id: <E1vlmF2-00000006zoO-3KhH@rmk-PC.armlinux.org.uk>
Date: Fri, 30 Jan 2026 11:00:44 +0000
From: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
To: Andrew Lunn <andrew@...n.ch>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Heiko Stuebner <heiko@...ech.de>,
Jakub Kicinski <kuba@...nel.org>,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com,
netdev@...r.kernel.org,
Paolo Abeni <pabeni@...hat.com>
Subject: [PATCH net-next 07/10] net: stmmac: rk: use rk_encode_wm16() for RMII
speed
The RMII speed configuration is encoded as a single bit, which is set
for 100M and clean for 10M. Provide the bitfield definition in
struct rk_clock_fields, moving it out of struct rk_reg_speed_data's
rmii_10 and rmii_100 initialisers. Update rk_set_reg_speed() to handle
the new definition location of this bit.
Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 69 +++++++++----------
1 file changed, 31 insertions(+), 38 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index e9d2f982b658..109add21a6c8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -28,6 +28,7 @@ struct rk_priv_data;
struct rk_clock_fields {
u16 gmii_clk_sel_mask;
+ u16 mac_speed_mask;
};
struct rk_reg_speed_data {
@@ -184,10 +185,12 @@ static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
} else if (interface == PHY_INTERFACE_MODE_RMII) {
+ val = rk_encode_wm16(speed == SPEED_100,
+ bsp_priv->clock.mac_speed_mask);
if (speed == SPEED_10) {
- val = rsd->rmii_10;
+ val |= rsd->rmii_10;
} else if (speed == SPEED_100) {
- val = rsd->rmii_100;
+ val |= rsd->rmii_100;
} else {
/* Phylink will not allow inappropriate speeds for
* interface modes, so this should never happen.
@@ -364,8 +367,6 @@ static const struct rk_gmac_ops px30_ops = {
/* RK3128_GRF_MAC_CON1 */
#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
-#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
@@ -383,8 +384,8 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3128_reg_speed_data = {
- .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M,
- .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M,
+ .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3128_GMAC_RMII_CLK_25M,
};
static int rk3128_set_speed(struct rk_priv_data *bsp_priv,
@@ -405,6 +406,7 @@ static const struct rk_gmac_ops rk3128_ops = {
.clock_grf_reg = RK3128_GRF_MAC_CON1,
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
+ .clock.mac_speed_mask = BIT_U16(10),
};
#define RK3228_GRF_MAC_CON0 0x0900
@@ -419,8 +421,6 @@ static const struct rk_gmac_ops rk3128_ops = {
/* RK3228_GRF_MAC_CON1 */
#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -449,8 +449,8 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3228_reg_speed_data = {
- .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M,
- .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M,
+ .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3228_GMAC_RMII_CLK_25M,
};
static int rk3228_set_speed(struct rk_priv_data *bsp_priv,
@@ -481,6 +481,7 @@ static const struct rk_gmac_ops rk3228_ops = {
.clock_grf_reg = RK3228_GRF_MAC_CON1,
.clock.gmii_clk_sel_mask = GENMASK_U16(9, 8),
+ .clock.mac_speed_mask = BIT_U16(2),
};
#define RK3288_GRF_SOC_CON1 0x0248
@@ -489,8 +490,6 @@ static const struct rk_gmac_ops rk3228_ops = {
/*RK3288_GRF_SOC_CON1*/
#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
-#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
@@ -516,8 +515,8 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3288_reg_speed_data = {
- .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M,
- .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M,
+ .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3288_GMAC_RMII_CLK_25M,
};
static int rk3288_set_speed(struct rk_priv_data *bsp_priv,
@@ -538,6 +537,7 @@ static const struct rk_gmac_ops rk3288_ops = {
.clock_grf_reg = RK3288_GRF_SOC_CON1,
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
+ .clock.mac_speed_mask = BIT_U16(10),
};
#define RK3308_GRF_MAC_CON0 0x04a0
@@ -545,16 +545,12 @@ static const struct rk_gmac_ops rk3288_ops = {
/* RK3308_GRF_MAC_CON0 */
#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
-#define RK3308_GMAC_SPEED_100M GRF_BIT(0)
static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
static const struct rk_reg_speed_data rk3308_reg_speed_data = {
- .rmii_10 = RK3308_GMAC_SPEED_10M,
- .rmii_100 = RK3308_GMAC_SPEED_100M,
};
static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
@@ -572,6 +568,7 @@ static const struct rk_gmac_ops rk3308_ops = {
.gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
.clock_grf_reg = RK3308_GRF_MAC_CON0,
+ .clock.mac_speed_mask = BIT_U16(0),
};
#define RK3328_GRF_MAC_CON0 0x0900
@@ -586,8 +583,6 @@ static const struct rk_gmac_ops rk3308_ops = {
/* RK3328_GRF_MAC_CON1 */
#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -632,8 +627,8 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3328_reg_speed_data = {
- .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M,
- .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M,
+ .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3328_GMAC_RMII_CLK_25M,
};
static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
@@ -662,6 +657,8 @@ static const struct rk_gmac_ops rk3328_ops = {
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
.gmac_rmii_mode_mask = BIT_U16(9),
+ .clock.mac_speed_mask = BIT_U16(2),
+
.regs_valid = true,
.regs = {
0xff540000, /* gmac2io */
@@ -676,8 +673,6 @@ static const struct rk_gmac_ops rk3328_ops = {
/* RK3366_GRF_SOC_CON6 */
#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
@@ -703,8 +698,8 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3366_reg_speed_data = {
- .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M,
- .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M,
+ .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3366_GMAC_RMII_CLK_25M,
};
static int rk3366_set_speed(struct rk_priv_data *bsp_priv,
@@ -725,6 +720,7 @@ static const struct rk_gmac_ops rk3366_ops = {
.clock_grf_reg = RK3366_GRF_SOC_CON6,
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .clock.mac_speed_mask = BIT_U16(7),
};
#define RK3368_GRF_SOC_CON15 0x043c
@@ -733,8 +729,6 @@ static const struct rk_gmac_ops rk3366_ops = {
/* RK3368_GRF_SOC_CON15 */
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
@@ -760,8 +754,8 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3368_reg_speed_data = {
- .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M,
- .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M,
+ .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3368_GMAC_RMII_CLK_25M,
};
static int rk3368_set_speed(struct rk_priv_data *bsp_priv,
@@ -782,6 +776,7 @@ static const struct rk_gmac_ops rk3368_ops = {
.clock_grf_reg = RK3368_GRF_SOC_CON15,
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .clock.mac_speed_mask = BIT_U16(7),
};
#define RK3399_GRF_SOC_CON5 0xc214
@@ -790,8 +785,6 @@ static const struct rk_gmac_ops rk3368_ops = {
/* RK3399_GRF_SOC_CON5 */
#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
@@ -817,8 +810,8 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3399_reg_speed_data = {
- .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M,
- .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M,
+ .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3399_GMAC_RMII_CLK_25M,
};
static int rk3399_set_speed(struct rk_priv_data *bsp_priv,
@@ -839,6 +832,7 @@ static const struct rk_gmac_ops rk3399_ops = {
.clock_grf_reg = RK3399_GRF_SOC_CON5,
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .clock.mac_speed_mask = BIT_U16(7),
};
#define RK3506_GRF_SOC_CON8 0x0020
@@ -1384,8 +1378,6 @@ static const struct rk_gmac_ops rk3588_ops = {
/* RV1108_GRF_GMAC_CON0 */
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RV1108_GMAC_SPEED_100M GRF_BIT(2)
#define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
@@ -1394,8 +1386,8 @@ static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rv1108_reg_speed_data = {
- .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M,
- .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M,
+ .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RV1108_GMAC_RMII_CLK_25M,
};
static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
@@ -1413,6 +1405,7 @@ static const struct rk_gmac_ops rv1108_ops = {
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
.clock_grf_reg = RV1108_GRF_GMAC_CON0,
+ .clock.mac_speed_mask = BIT_U16(2),
};
#define RV1126_GRF_GMAC_CON0 0X0070
--
2.47.3
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