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Message-Id: <20260130141035.272471-1-claudiu.manoil@nxp.com>
Date: Fri, 30 Jan 2026 16:10:31 +0200
From: Claudiu Manoil <claudiu.manoil@....com>
To: vladimir.oltean@....com,
wei.fang@....com,
xiaoning.wang@....com,
Frank.Li@....com
Cc: kuba@...nel.org,
davem@...emloft.net,
andrew+netdev@...n.ch,
edumazet@...gle.com,
pabeni@...hat.com,
imx@...ts.linux.dev,
netdev@...r.kernel.org
Subject: [PATCH net 0/4] ENETC v4 hardware integration fixes
ENETC v4 targeted fixes addressing SoC level integration issues
regarding AXI settings and register access width.
Claudiu Manoil (4):
net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4
net: enetc: Remove CBDR cacheability AXI settings for ENETC v4
net: enetc: Convert 16-bit register writes to 32-bit for ENETC v4
net: enetc: Convert 16-bit register reads to 32-bit for ENETC v4
drivers/net/ethernet/freescale/enetc/enetc.c | 11 +++++++----
.../net/ethernet/freescale/enetc/enetc4_pf.c | 6 +++---
.../net/ethernet/freescale/enetc/enetc_cbdr.c | 4 ----
drivers/net/ethernet/freescale/enetc/enetc_hw.h | 17 ++++++++++++++---
4 files changed, 24 insertions(+), 14 deletions(-)
--
2.34.1
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