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Message-Id: <20260130141035.272471-3-claudiu.manoil@nxp.com>
Date: Fri, 30 Jan 2026 16:10:33 +0200
From: Claudiu Manoil <claudiu.manoil@....com>
To: vladimir.oltean@....com,
wei.fang@....com,
xiaoning.wang@....com,
Frank.Li@....com
Cc: kuba@...nel.org,
davem@...emloft.net,
andrew+netdev@...n.ch,
edumazet@...gle.com,
pabeni@...hat.com,
imx@...ts.linux.dev,
netdev@...r.kernel.org
Subject: [PATCH net 2/4] net: enetc: Remove CBDR cacheability AXI settings for ENETC v4
For ENETC v4 these settings are controlled by the global ENETC
command cache attribute registers (EnCAR), from the IERB register
block.
The hardcoded CDBR cacheability settings were inherited from LS1028A,
and should be removed from the ENETC v4 driver as they conflict
with the global IERB settings.
Fixes: e3f4a0a8ddb4 ("net: enetc: add command BD ring support for i.MX95 ENETC")
Signed-off-by: Claudiu Manoil <claudiu.manoil@....com>
---
drivers/net/ethernet/freescale/enetc/enetc_cbdr.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
index 3d5f31879d5c..a635bfdc30af 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
@@ -74,10 +74,6 @@ int enetc4_setup_cbdr(struct enetc_si *si)
if (!user->ring)
return -ENOMEM;
- /* set CBDR cache attributes */
- enetc_wr(hw, ENETC_SICAR2,
- ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
-
regs.pir = hw->reg + ENETC_SICBDRPIR;
regs.cir = hw->reg + ENETC_SICBDRCIR;
regs.mr = hw->reg + ENETC_SICBDRMR;
--
2.34.1
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