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Message-ID: <81407a61-1e6a-436c-83f3-fc403a706af6@gmail.com>
Date: Tue, 3 Feb 2026 21:13:47 +0100
From: Heiner Kallweit <hkallweit1@...il.com>
To: javen <javen_xu@...lsil.com.cn>
Cc: andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
horms@...nel.org, kuba@...nel.org, linux-kernel@...r.kernel.org,
netdev@...r.kernel.org, nic_swsd@...ltek.com, pabeni@...hat.com
Subject: Re: [PATCH net-next v3] r8169: add support for RTL8125cp
On 2/3/2026 8:58 AM, javen wrote:
>> On 2/2/2026 11:58 AM, javen wrote:
>
>>> From: Javen Xu <javen_xu@...lsil.com.cn>
>
>>>
>
>>> This patch adds support for chip RTL8125cp. Its XID is 0x708. We apply
>
>>> different and firmware for RTL8125cp.
>
>>>
>
>>> Signed-off-by: Javen Xu <javen_xu@...lsil.com.cn>
>
>>>
>
>>> ---
>
>>> v2: This patch fix one mistake on phy_modify_paged(phydev, 0xa43,
>
>>> 0x10, 0x0000, 0x1001) which is phy_modify_paged(phydev, 0xa43, 0x00, 0x0000, 0x1001) on patch v1.
>
>>>
>
>>> v3: Set phy_modify_paged(phydev, 0xa43, 0x10, 0x0000, 0x0003), bit 0
>
>>> means 'link speed 10m PLL OFF', bit 1 means 'ALDPS PLL OFF', bit 2
>
>>> means 'ENABLE ALDPS', bit 12 means 'ALDPS XTAL OFF'.
>
>>
>
>> ALDPS is disabled two lines later in rtl8125cp_hw_phy_config().
>
>> So why bother with ALDPS settings if ALDPS is disabled anyway?
>
>
>
> Bit 2 means 'ENABLE ALDPS', we prefer to treat it as a master switch that controls
>
> some sub-features like bit 1(ALDPS PLL OFF) and bit 12(ALDPS XTAL OFF), instead of
>
> controlling these sub-features individually. And bit 0(link speed 10m PLL OFF)
>
> has noting to do with aldps.
>
I see, you changed the value of a43/10 to 0x0003 in v3. Then just this question:
Few lines later ALDPS gets disabled, so is it beneficial to set bit 1 here?
Thanks for mentioning that bit 0 isn't related to ALDPS.
>
>
> Thanks,
>
> Javen Xu
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