netdev - Re: [PATCH v5 01/18] dt-bindings: clock: Add MediaTek MT8189 clock

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Message-ID: <dfd2801b-75dd-48eb-9e87-2b88fc00b66e@lechnology.com>
Date: Tue, 3 Feb 2026 16:07:19 -0600
From: David Lechner <david@...hnology.com>
To: "irving.ch.lin" <irving-ch.lin@...iatek.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>,
 AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
 Richard Cochran <richardcochran@...il.com>,
 Bartosz Golaszewski <brgl@...nel.org>, Chen-Yu Tsai <wenst@...omium.org>,
 Miles Chen <miles.chen@...iatek.com>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org,
 Project_Global_Chrome_Upstream_Group@...iatek.com,
 Qiqi Wang <qiqi.wang@...iatek.com>, sirius.wang@...iatek.com,
 vince-wl.liu@...iatek.com, jh.hsu@...iatek.com
Subject: Re: [PATCH v5 01/18] dt-bindings: clock: Add MediaTek MT8189 clock

On 2/2/26 12:28 AM, irving.ch.lin wrote:
> From: Irving-CH Lin <irving-ch.lin@...iatek.com>
> 
> Add dt schema and IDs for the clocks of MediaTek MT8189 SoC.
> The MT8189 clock IP provide clock control for main system
> (apmixedsys, topcksys and vlpcksys) and
> subsys (eg. peri, mfg, venc/vdec ...).
> 

> +#define CLK_TOP_VOWPLL                                  174
This one seems out of place. It is not used in the driver. It is
a fixed 1:1 divider AFAKCT, so should not be included. (And this
line has spaces while the rest of the file uses tabs for indent.)