lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
 <TY3PR01MB11346D903D0F00F167DE25FE58698A@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Wed, 4 Feb 2026 21:40:31 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: biju.das.au <biju.das.au@...il.com>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, biju.das.au
	<biju.das.au@...il.com>, Conor Dooley <conor.dooley@...rochip.com>
Subject: RE: [PATCH v2] dt-bindings: net: renesas,rzv2h-gbeth: Document
 Renesas RZ/G3L RMII{tx,rx} clocks To: Lad Prabhakar
 <prabhakar.mahadev-lad.rj@...renesas.com>, Andrew Lunn
 <andrew+netdev@...n.ch>, "David S. Miller" <davem@...emloft.net>, Eric
 Dumazet <eduma

Hi all,

Please ignore this patch, as the patch header got corrupted.

I have sent another patch fixing this[1]. Sorry for the noise.

[1] https://lore.kernel.org/all/20260204213524.3437-1-biju.das.jz@bp.renesas.com/

Cheers,
Biju

> -----Original Message-----
> From: Biju <biju.das.au@...il.com>
> Sent: 04 February 2026 21:26
> Cc: Biju Das <biju.das.jz@...renesas.com>; netdev@...r.kernel.org; linux-renesas-soc@...r.kernel.org;
> devicetree@...r.kernel.org; linux-kernel@...r.kernel.org; biju.das.au <biju.das.au@...il.com>; Conor
> Dooley <conor.dooley@...rochip.com>
> Subject: [PATCH v2] dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/G3L RMII{tx,rx} clocks
> To: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, Andrew Lunn <andrew+netdev@...n.ch>,
> "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumaz...
> 
> From: Biju Das <biju.das.jz@...renesas.com>
> 
> As per the RZ/G3L Hardware manual, CPG_CLKON_ETH register bits{12,13} are to control the RMII{tx, rx}
> clocks. Document the RMII{tx, rx} clocks for RZ/G3L SoC.
> 
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> Fixes: 3ac2aa31b489eb4e ("dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/G3L SoC")
> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> ---
> v1->v2:
>  * Collected tag
>  * Added Fixes tag
>  * Fixed typo {tx.rx}->{tx, rx} in xommit description.
> ---
>  .../devicetree/bindings/net/renesas,rzv2h-gbeth.yaml      | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
> b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
> index fb60f745a1ff..2125b5ddf73d 100644
> --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
> +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
> @@ -58,6 +58,8 @@ properties:
>            - description: TX clock phase-shifted by 180 degrees
>            - description: RX clock phase-shifted by 180 degrees
>            - description: RMII clock
> +          - description: RMII TX clock
> +          - description: RMII RX clock
> 
>          minItems: 7
> 
> @@ -77,6 +79,8 @@ properties:
>            - const: tx-180
>            - const: rx-180
>            - const: rmii
> +          - const: rmii_tx
> +          - const: rmii_rx
> 
>          minItems: 7
> 
> @@ -170,10 +174,10 @@ allOf:
>      then:
>        properties:
>          clocks:
> -          minItems: 8
> +          minItems: 10
> 
>          clock-names:
> -          minItems: 8
> +          minItems: 10
> 
>          interrupts:
>            minItems: 15
> --
> 2.43.0


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ