phc-discussions - Re: [PHC] many-core archs (Re: [PHC] ASICs)

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Sat, 11 Jan 2014 17:10:48 -0500
From: Bill Cox <waywardgeek@...il.com>
To: discussions@...sword-hashing.net
Subject: Re: [PHC] many-core archs (Re: [PHC] ASICs)

On Fri, Jan 10, 2014 at 11:13 PM, Solar Designer <solar@...nwall.com> wrote:
> Actually, we had two Google Summer of Code projects last year,
> implementing bcrypt and Litecoin (scrypt at 128 KB) on Epiphany.
> We got reasonably good performance numbers for bcrypt.  For E64, they're
> on par with common CPUs and GPUs, but at much lower energy consumption:

Sweet.

>> Grid based multi-CPU companies seem to come along
>> every few years.  I hope they do well, but the always seem to be a
>> solution looking for a problem.  Maybe they can sell a bunch to
>> governments for password cracking?
>
> Maybe, although I'd be happier with them satisfying commercial demand,
> even if also for password cracking.  I think what's missing are PCIe
> boards with multiple energy-efficient many-core chips per board.  Then
> they'd be able to compete not only in terms of energy efficiency, but
> also in terms of raw performance per board - for suitable tasks only,
> though.  I did discuss this with Andreas, and he agrees.
>
> Another company - Kalray - recently released a PCIe board with their
> 288-core chip, but it also has only one such chip, and it is pricey:
>
> http://www.kalray.eu/news-7/news/kalray-launches-mppa-board-emb01-its-first-mppa-r-based-embedded-board
> http://www.kalray.eu/products/mppa-board/mppa-board-emb01/
> http://www.kalray.eu/technology/
>
> Regarding the 256 vs. 288 cores confusion, their replies on Twitter:
>
> <@Kalray1> @solardiz The MPPA256 has in reality 288 cores !  This brings 288*0.4*(1 branch + 2 ALU + 1 load/store + 1 FMA counted as 2) = 691.2 GOPS !
> <@Kalray1> @solardiz  The MPPA256 has in reality 288 cores ! This brings  288*0.4*( 1 FMA counted as 2) = 230 GFLOPS !
> <@Kalray1> @solardiz 16 clusters of 17 cores + 4 quad-cores in the IOs subsystems.
>
> Then there's Tilera, which I think is doing pretty well targeting the
> high-speed networking market, providing solutions for traffic monitoring
> and DPI (nasty!) and maybe also IDS/IPS and potentially anti-DDoS:
>
> http://tilera.com
>
> And there's XMOS, but it's about realtime rather than high performance,
> so sort of an alternative to small FPGAs (not good for password cracking):
>
> http://www.xmos.com
>
> I guess you knew these, but I thought others on this mailing list might
> appreciate a summary of current many-core/MIMD archs.

No, I hadn't heard of them.  Are they newish since the end of the
recession?  I've been buried in analog synthesis since then.  I try to
stay current with FPGA and structured ASIC technology.  The last new
startup I was involved with, other than my current company, Triad
Semiconductor, (who bought ViASIC), was Achronix, where I helped tune
their routing a bit.  I haven't seen a new FPGA or structured ASIC
company in a while.

Thanks for the links.  I'm still trying to get my head around
multi-processing in an XMOS microcontroller, but the others all seem
to be massively parallel computation engines.  Is there anything else
I should know about them?

Bill