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Date: Sun, 09 Feb 2014 06:18:20 +0000
From: Samuel Neves <sneves@....uc.pt>
To: discussions@...sword-hashing.net
Subject: Re: [PHC] multiply-hardening (Re: NoelKDF ready for submission)

On 09-02-2014 04:26, Bill Cox wrote:
> By the way, if you're familiar with results from skilled hand layout
> of such circuits in advanced IC processes, I'd love to hear your
> thoughts on Salsa20/8 latency with a custom hand-optimized layout in
> the fastest processes.

Sorry, can't help you there; my knowledge is limited to the software
side of things. That said, your estimate does look reasonable: [1]
reports 4 cycles (one cycle per double-round) for the highest-area
implementation, 8 cycles at roughly half the area, or 32 cycles at 1/4th
of the area. The most efficient (in throughput/gates) is the second choice.

[1] http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=4746906

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