phc-discussions - Re: [PHC] die area estimates (Re: [PHC] GPU multiplication speed?)

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Message-ID: <20140227163629.GA12502@openwall.com>
Date: Thu, 27 Feb 2014 20:36:29 +0400
From: Solar Designer <solar@...nwall.com>
To: discussions@...sword-hashing.net
Subject: Re: [PHC] die area estimates (Re: [PHC] GPU multiplication speed?)

On Thu, Feb 27, 2014 at 08:15:51PM +0400, Solar Designer wrote:
> If we estimate 1 bit of SRAM to be roughly the same as a 1-bit full
> adder

Wikipedia gives 6 transistors for 1 bit of SRAM vs. 28 for 1 full adder:

http://en.wikipedia.org/wiki/Transistor_count

The smallest full adder I heard of (half-analog, weird) is 4 transistors
plus 4 diodes (and other components):

http://3.14.by/en/read/BarsFA-4T-full-adder

It's probably not suitable for high-speed ASIC.  (I'm toying with the
idea of actually trying it on a breadboard.)

Using canonical estimates for transistor count, a 32x32->64 multiplier
is more like a 4 KiB SRAM.

Alexander