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Date: Thu, 27 Feb 2014 21:42:12 -0500
From: Bill Cox <>
Subject: Re: [PHC] die area estimates (Re: [PHC] GPU multiplication speed?)

On Thu, Feb 27, 2014 at 9:10 PM, Solar Designer <> wrote:
> It might make more sense against attacks with other CPU-like devices,
> some of which might be smaller than the defender's (or have relatively
> fewer multipliers per L1 cache size) - e.g., a botnet of smartphones.
> Alexander

I keep thinking that with your GPU background and experience with
other multi-core devices, that you've got some totally awesome
massively parallel password authentication machine in mind, where the
multipliers and ALU logic add up to a lot even compared to the RAM.

It would be fun :-)

The funny thing about Moore's Law is humans, even really bright guys,
are almost incapable of having a good gut feel for it.  I remember in
grammar school they used to amaze us with how much a dollar used to
buy.  Now I'm shocked at how little it buys.  If you ask about
multiplier area in .35u, where my company still does a lot of analog,
I'd be thrilled to get 4,000 on a chip.  You get about 150X more
digital stuff in the same mm^2 in 28nm than we do in .35u.  This is
why there's such a huge difference in estimates for the cost of an
ASIC.  Did you mean a .35u ASIC, or a cutting edge 28nm ASIC?  One
reason mask costs for 28nm are so much higher is that e-beam writing
costs the same per distance traveled.  A 28nm reticle has 12-ish times
longer lines per reticle, and more reticles as well.  A 10X difference
in mask costs alone is normal.  Then there's the engineering cost...
sadly, it often costs about 100X more in engineering hours to design a
chip with 100X more transistors.  Thankfully, we can always just make
the RAMs bigger!


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