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Date: Wed, 1 Apr 2015 21:57:11 +0300
From: Solar Designer <>
Subject: Re: [PHC] Compute time hardness

On Wed, Apr 01, 2015 at 07:12:24PM +0100, Samuel Neves wrote:
> You can certainly do the n^2 ANDs and add things up, but that seems like a waste of gates. What is the cost metric being
> considered here? Time (circuit depth)? Area? Time * Area?

Time (circuit depth).  We're using MULs for latency hardening, so our
worst case attacker would optimize for lower latency.

> As a theoretical curiosity, Brent and Kung [1] came up with an optimal area-time n-bit multiplier of depth O(n^(1/2) log
> n) and area O(n log n). Melhorn-Preparata's [2] circuit would be O(log n), O(n^2 / log n).


> The above would be (asymptotically) depth O(log n) and area O(n^2).


> [1]
> [2]


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