phc-discussions - Re: [PHC] Compute time hardness

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Fri, 3 Apr 2015 15:13:06 +0300
From: Solar Designer <solar@...nwall.com>
To: discussions@...sword-hashing.net
Subject: Re: [PHC] Compute time hardness

Here's another relevant detail I recalled:

Pentium 4 (some or all of them? not sure) had double-pumped ALU, where
it could perform ADDs at double the clock rate (so up to 7.6 GHz, at
stock clocks).

http://www.anandtech.com/show/1611/7
http://forums.anandtech.com/showthread.php?t=603812
https://news.ycombinator.com/item?id=8255157
http://en.wikipedia.org/wiki/NetBurst_(microarchitecture)#Rapid_Execution_Engine

Apparently, this could only execute two dependent ADDs in a cycle if
they are 16-bit each.  To me, this indicates that an ASIC would probably
be able to do similar for 32-bit if it wanted to.

So I think this confirms 8x-ish difference in latency between fastest
ADD and MUL.

Alexander